Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10761137 | Flexible manufacturing flow enabled by adaptive binning system | Lee N. Chung, Arnold Louie, Dahshi Shen, Felino E. Pagaduan, Tony Le | 2020-09-01 |
| 8030954 | Internal voltage level shifting for screening cold or hot temperature defects using room temperature testing | Srinivasa R. Parthasarathy, Lee N. Chung, Jian Shi | 2011-10-04 |
| 7583102 | Testing of input/output devices of an integrated circuit | Tuyet Ngoc Simmons, Andy T. Nguyen, Andrew W. Lai, Shankar Lakkapragada | 2009-09-01 |
| 7558995 | Method and apparatus for eliminating noise induced errors during test of a programmable logic device | Teymour M. Mansour | 2009-07-07 |
| 7262623 | Method for gross I/O functional test at wafer sort | David Mark, Yung-Cheng Chen | 2007-08-28 |
| 7124338 | Methods of testing interconnect lines in programmable logic devices using partial reconfiguration | David Mark, Huy Le, Kazi S. Afzal | 2006-10-17 |
| 6943581 | Test methodology for direct interconnect with multiple fan-outs | Arnold A. Cruz | 2005-09-13 |
| 6944809 | Methods of resource optimization in programmable logic devices to reduce test time | Andrew W. Lai, Teymour M. Mansour, Vincent L. Tong, Jeffrey V. Lindholm, Jay T. Young +2 more | 2005-09-13 |
| 6889368 | Method and apparatus for localizing faults within a programmable logic device | David Mark, Min Luo | 2005-05-03 |
| 6788095 | Method for gross input leakage functional test at wafer sort | David Mark | 2004-09-07 |