Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10715149 | Configurable logic block (CLB) internal routing architecture for enhanced local routing and clocking improvements | Eric F. Dellinger, Brian C. Gaide, Chirag Ravishankar, Davis Boyd MOORE, Steven P. Young | 2020-07-14 |
| 10467373 | Method of selecting routing resources in a multi-chip integrated circuit device | — | 2019-11-05 |
| 8418221 | Methods of prioritizing routing resources to generate and evaluate test designs in programmable logic devices | Ian L. McEwen | 2013-04-09 |
| 8332788 | Generating a module interface for partial reconfiguration design flows | W. Story Leavesley, III | 2012-12-11 |
| 7941777 | Generating a module interface for partial reconfiguration design flows | W. Story Leavesley, III | 2011-05-10 |
| 7890917 | Method and apparatus for providing secure intellectual property cores for a programmable logic device | Jeffrey M. Mason | 2011-02-15 |
| 7673272 | Method and apparatus for generating an area constraint for a module in a programmable logic device | — | 2010-03-02 |
| 7600210 | Method and apparatus for modular circuit design for a programmable logic device | Jeffrey M. Mason | 2009-10-06 |
| 7509617 | Design methodology to support relocatable bit streams for dynamic partial reconfiguration of FPGAs to reduce bit stream memory requirements | — | 2009-03-24 |
| 7480842 | Method and apparatus for reducing the number of test designs for device testing | Ian L. McEwen, Reto Stamm | 2009-01-20 |
| 7299430 | Reducing design execution run time bit stream size for device testing | Ian L. McEwen | 2007-11-20 |
| 7249335 | Methods of routing programmable logic devices to minimize programming time | Jeffrey V. Lindholm, Sridhar Krishnamurthy | 2007-07-24 |
| 7149997 | Routing with frame awareness to minimize device programming time and test cost | Jeffrey V. Lindholm, Ian L. McEwen | 2006-12-12 |
| 7143384 | Methods of routing programmable logic devices to minimize programming time | Jeffrey V. Lindholm, Sridhar Krishnamurthy | 2006-11-28 |
| 7058919 | Methods of generating test designs for testing specific routing resources in programmable logic devices | Sridhar Krishnamurthy, Jeffrey V. Lindholm, Ian L. McEwen | 2006-06-06 |
| 6944809 | Methods of resource optimization in programmable logic devices to reduce test time | Andrew W. Lai, Randy J. Simmons, Teymour M. Mansour, Vincent L. Tong, Jeffrey V. Lindholm +2 more | 2005-09-13 |
| 6760899 | Dedicated resource placement enhancement | Salim Abid | 2004-07-06 |
| 5659484 | Frequency driven layout and method for field programmable gate arrays | David W. Bennett, Eric F. Dellinger, Walter A. Manaker, Jr., Carl M. Stern, William R. Troxel | 1997-08-19 |
| 5648913 | Frequency driven layout system and method for field programmable gate arrays | David W. Bennett, Eric F. Dellinger, Walter A. Manaker, Jr., Carl M. Stern, William R. Troxel | 1997-07-15 |