Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9378003 | Compiler directed cache coherence for many caches generated from high-level language source code | Prasanna Sundararajan, Andrew R. Putnam | 2016-06-28 |
| 8868833 | Processor and cache arrangement with selective caching between first-level and second-level caches | David W. Bennett | 2014-10-21 |
| 8839004 | Secure cloud computing infrastructure | David W. Bennett | 2014-09-16 |
| 8473904 | Generation of cache architecture from a high-level language description | Prasanna Sundararajan, David W. Bennett, Robert Gwilym Dimond, Lauren B. Wenzl | 2013-06-25 |
| 7930662 | Methods for automatically generating fault mitigation strategies for electronic system designs | Prasanna Sundararajan, John D. Corbett, David W. Bennett | 2011-04-19 |
| 7917567 | Floating-point processing unit for successive floating-point operations | David W. Bennett | 2011-03-29 |
| 7890917 | Method and apparatus for providing secure intellectual property cores for a programmable logic device | Jay T. Young | 2011-02-15 |
| 7817655 | Determining sizes of FIFO buffers between functional blocks in an electronic circuit | David W. Bennett | 2010-10-19 |
| 7619442 | Versatile bus interface macro for dynamically reconfigurable designs | W. Story Leavesley, III | 2009-11-17 |
| 7600210 | Method and apparatus for modular circuit design for a programmable logic device | Jay T. Young | 2009-10-06 |
| 7478357 | Versatile bus interface macro for dynamically reconfigurable designs | W. Story Leavesley, III | 2009-01-13 |
| 7086029 | Incremental design using a group area designation | Arne S. Barras, Kate L. Kelley | 2006-08-01 |
| 6817005 | Modular design method and system for programmable logic devices | Steve E. Lass, Bruce E. Talley, David W. Bennett | 2004-11-09 |