Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12393480 | Reclamation of memory ECC bits for error tolerant number formats | Zachary Blair, Alireza Khodamoradi, Ralph D. Wittig, Kristof Denolf | 2025-08-19 |
| 12307217 | Dynamic adjustment of floating point exponent bias for exponent compression | Philip B. James-Roxby | 2025-05-20 |
| 11824564 | Lossless compression using subnormal floating point values | Philip B. James-Roxby | 2023-11-21 |
| 11216275 | Converting floating point data into integer data using a dynamically adjusted scale factor | Philip B. James-Roxby | 2022-01-04 |
| 10715149 | Configurable logic block (CLB) internal routing architecture for enhanced local routing and clocking improvements | Jay T. Young, Brian C. Gaide, Chirag Ravishankar, Davis Boyd MOORE, Steven P. Young | 2020-07-14 |
| 10042806 | System-level interconnect ring for a programmable integrated circuit | Alireza S. Kaviani, Pongstorn Maidee | 2018-08-07 |
| 9859896 | Distributed multi-die routing in a multi-chip module | Brian C. Gaide, Steven P. Young | 2018-01-02 |
| 8504950 | Modular array defined by standard cell logic | — | 2013-08-06 |
| 7770144 | Modular array defined by standard cell logic | — | 2010-08-03 |
| 7648912 | ASIC customization with predefined via mask | — | 2010-01-19 |
| 7102237 | ASIC customization with predefined via mask | — | 2006-09-05 |
| 6885043 | ASIC routing architecture | Lyle Smith, Eric T. West, Shridhar Mukund | 2005-04-26 |
| 6696856 | Function block architecture with variable drive strengths | Lyle Smith, Eric T. West, Shridhar Mukund | 2004-02-24 |
| 6613611 | ASIC routing architecture with variable number of custom masks | Dana How, Robert Osann, Jr. | 2003-09-02 |
| 6457164 | Hetergeneous method for determining module placement in FPGAs | L. James Hwang, Sujoy Mitra, Sundararajarao Mohan, Cameron Patterson, Ralph D. Wittig | 2002-09-24 |
| 6292925 | Context-sensitive self implementing modules | L. James Hwang, Sujoy Mitra, Sundararajarao Mohan, Ralph D. Wittig | 2001-09-18 |
| 6260182 | Method for specifying routing in a logic module by direct module communication | Sundararajarao Mohan, L. James Hwang, Sujoy Mitra, Ralph D. Wittig | 2001-07-10 |
| 6243851 | Heterogeneous method for determining module placement in FPGAs | L. James Hwang, Sujoy Mitra, Sundararajarao Mohan, Cameron Patterson, Ralph D. Wittig | 2001-06-05 |
| 6237129 | Method for constraining circuit element positions in structured layouts | Cameron Patterson, L. James Hwang, Sujoy Mitra, Sundararajarao Mohan, Ralph D. Wittig | 2001-05-22 |
| 6216258 | FPGA modules parameterized by expressions | Sundararajarao Mohan, L. James Hwang, Sujoy Mitra, Ralph D. Wittig | 2001-04-10 |
| 6205574 | Method and system for generating a programming bitstream including identification bits | Roman Iwanczuk | 2001-03-20 |
| 5659484 | Frequency driven layout and method for field programmable gate arrays | David W. Bennett, Walter A. Manaker, Jr., Carl M. Stern, William R. Troxel, Jay T. Young | 1997-08-19 |
| 5648913 | Frequency driven layout system and method for field programmable gate arrays | David W. Bennett, Walter A. Manaker, Jr., Carl M. Stern, William R. Troxel, Jay T. Young | 1997-07-15 |