Issued Patents All Time
Showing 25 most recent of 56 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12393480 | Reclamation of memory ECC bits for error tolerant number formats | Zachary Blair, Alireza Khodamoradi, Eric F. Dellinger, Kristof Denolf | 2025-08-19 |
| 11972132 | Data processing engine arrangement in a device | Juan J. Noguera Serra, Goran H K Bilski, Jan Langer, Baris Ozgul, Richard L. Walke +3 more | 2024-04-30 |
| 11687327 | Control and reconfiguration of data flow graphs on heterogeneous computing platform | Chia-Jui Hsu, Shail Aditya Gupta, Samuel R. Bayliss, Philip B. James-Roxby, Vinod K. Kathail | 2023-06-27 |
| 11573726 | Data processing engine arrangement in a device | Juan J. Noguera Serra, Goran H K Bilski, Jan Langer, Baris Ozgul, Richard L. Walke +3 more | 2023-02-07 |
| 11281440 | Control and reconfiguration of data flow graphs on heterogeneous computing platform | Chia-Jui Hsu, Shail Aditya Gupta, Samuel R. Bayliss, Philip B. James-Roxby, Vinod K. Kathail | 2022-03-22 |
| 11204745 | Dataflow graph programming environment for a heterogenous processing system | Shail Aditya Gupta, Samuel R. Bayliss, Vinod K. Kathail, Philip B. James-Roxby, Akella Sastry | 2021-12-21 |
| 10990552 | Streaming interconnect architecture for data processing engine array | Goran H K Bilski, Peter McColgan, Juan J. Noguera Serra, Baris Ozgul, Jan Langer +4 more | 2021-04-27 |
| 10866753 | Data processing engine arrangement in a device | Juan J. Noguera Serra, Goran H K Bilski, Jan Langer, Baris Ozgul, Tim Tuan +3 more | 2020-12-15 |
| 10860766 | Compilation flow for a heterogeneous multi-core architecture | Mukund Sivaraman, Shail Aditya Gupta, Akella Sastry, Rishi Surendran, Philip B. James-Roxby +3 more | 2020-12-08 |
| 10824434 | Dynamically structured single instruction, multiple data (SIMD) instructions | Sean Settle, Ehsan Ghasemi, Ashish Sirasao | 2020-11-03 |
| 10802807 | Control and reconfiguration of data flow graphs on heterogeneous computing platform | Chia-Jui Hsu, Shail Aditya Gupta, Samuel R. Bayliss, Philip B. James-Roxby, Vinod K. Kathail | 2020-10-13 |
| 10747690 | Device with data processing engine array | Goran H K Bilski, Juan J. Noguera Serra, Baris Ozgul, Jan Langer, Richard L. Walke +3 more | 2020-08-18 |
| 9846660 | Heterogeneous multiprocessor platform targeting programmable integrated circuits | Henry E. Styles, Jeffrey M. Fifield, Philip B. James-Roxby, Sonal Santan, Devadas Varma +3 more | 2017-12-19 |
| 9218443 | Heterogeneous multiprocessor program compilation targeting programmable integrated circuits | Henry E. Styles, Jeffrey M. Fifield, Philip B. James-Roxby, Sonal Santan, Devadas Varma +3 more | 2015-12-22 |
| 8479042 | Transaction-level lockstep | Philip B. James-Roxby | 2013-07-02 |
| 8447957 | Coprocessor interface architecture and methods of operating the same | Jorge Ernesto Carrillo, Navaneethan Sundaramoorthy, Sivakumar Velusamy, Vasanth Asokan | 2013-05-21 |
| 8443230 | Methods and systems with transaction-level lockstep | Philip B. James-Roxby, Brendan K. Bridgford, Robert M. McGee, Richard DeFelice | 2013-05-14 |
| 8352659 | Segmentation and reassembly of a data value communicated via interrupt transactions | Henry E. Styles, Richard S. Ballantyne, Mark Paluszkiewicz | 2013-01-08 |
| 8296557 | Providing multiple selectable configuration sources for programmable integrated circuits with fail safe mechanism | Richard S. Ballantyne, Mark Paluszkiewicz, Henry E. Styles | 2012-10-23 |
| 7948269 | System and method for open drain/open collector structures in an integrated circuit | Richard S. Ballantyne, Mark Paluszkiewicz, Henry E. Styles | 2011-05-24 |
| 7786762 | Generic buffer circuits and methods for out of band signaling | Richard S. Ballantyne, Catalin Baetoniu, Mark Paluszkiewicz, Henry E. Styles | 2010-08-31 |
| 7721090 | Event-driven simulation of IP using third party event-driven simulators | Kumar Deepak, Satish R. Ganesan, Jimmy Zhenming Wang, Sundararajarao Mohan, Hem C. Neema | 2010-05-18 |
| 7340585 | Method and system for fast linked processor in a system on a chip (SoC) | Satish R. Ganesan, Goran Bilski, Usha Prabhu | 2008-03-04 |
| 7310594 | Method and system for designing a multiprocessor | Satish R. Ganesan, Usha Prabhu, Sundararajarao Mohan, David W. Bennett | 2007-12-18 |
| 7248073 | Configurable logic element with expander structures | Bernard J. New, Sundararajarao Mohan | 2007-07-24 |