Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Shail Aditya Gupta — 30 Patents

HP: 16 patents #1,072 of 16,619Top 7%
AMD: 13 patents #982 of 9,280Top 15%
EIExcalibur Ip: 1 patents #198 of 667Top 30%
Sunnyvale, CA: #762 of 14,302 inventorsTop 6%
California: #17,345 of 386,348 inventorsTop 5%
Overall (All Time): #121,623 of 4,157,543Top 3%
30 Patents All Time
Shail Aditya Gupta has been granted 30 US patents while listed as an inventor at AMD. The first was granted in 2002 and the most recent in June 2023. Shail Aditya Gupta ranks #121,623 of 4,157,543 US inventors in our database (top 2.9%). Patent records list Shail Aditya Gupta in Sunnyvale, CA, US.

Patents per Year

Patents granted per year, 2002 to 2023Bar chart with a peak of 5 patents in 2021.peak 52002: 4 patents20022003: 4 patents2004: 1 patents20042005: 3 patents2006: 3 patents20062009: 1 patents2017: 1 patents20172020: 4 patents2021: 5 patents20212022: 2 patents2023: 2 patents2023

Issued Patents All Time

Showing 1–25 of 30 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
11687327 Control and reconfiguration of data flow graphs on heterogeneous computing platform Chia-Jui Hsu, Samuel R. Bayliss, Philip B. James-Roxby, Ralph D. Wittig, Vinod K. Kathail 2023-06-27
11645053 Hardware-software design flow with high-level synthesis for heterogeneous and programmable devices Akella Sastry, Vinod K. Kathail, L. James Hwang, Vidhumouli Hunsigida, Siddharth Rele 2023-05-09
11301295 Implementing an application specified as a data flow graph in an array of data processing engines Rishi Surendran 2022-04-12
11281440 Control and reconfiguration of data flow graphs on heterogeneous computing platform Chia-Jui Hsu, Samuel R. Bayliss, Philip B. James-Roxby, Ralph D. Wittig, Vinod K. Kathail 2022-03-22
11204745 Dataflow graph programming environment for a heterogenous processing system Samuel R. Bayliss, Vinod K. Kathail, Ralph D. Wittig, Philip B. James-Roxby, Akella Sastry 2021-12-21 $86,928,000
11188312 Hardware-software design flow with high-level synthesis for heterogeneous and programmable devices Akella Sastry, Vinod K. Kathail, L. James Hwang, Vidhumouli Hunsigida, Siddharth Rele 2021-11-30 $61,864,000
11113030 Constraints for applications in a heterogeneous programming environment Dinesh K. Monga, Samuel R. Bayliss, Kaushik Barman 2021-09-07 $55,935,000
10891414 Hardware-software design flow for heterogeneous and programmable devices Srinivas Beeravolu, Dinesh K. Monga, Pradip K. Jha, Vishal Suthar, Vinod K. Kathail +2 more 2021-01-12 $57,179,000
10891132 Flow convergence during hardware-software design for heterogeneous and programmable devices Rishi Surendran 2021-01-12 $57,179,000
10872057 Partitioning in a compiler flow for a heterogeneous multi-core architecture Prashant S. Rawat 2020-12-22 $97,972,000
10860766 Compilation flow for a heterogeneous multi-core architecture Mukund Sivaraman, Akella Sastry, Rishi Surendran, Philip B. James-Roxby, Samuel R. Bayliss +3 more 2020-12-08 $24,793,000
10802807 Control and reconfiguration of data flow graphs on heterogeneous computing platform Chia-Jui Hsu, Samuel R. Bayliss, Philip B. James-Roxby, Ralph D. Wittig, Vinod K. Kathail 2020-10-13 $57,700,000
10628622 Stream FIFO insertion in a compilation flow for a heterogeneous multi-core architecture Mukund Sivaraman, Abnikant Singh 2020-04-21 $30,775,000
9680893 Method and system for event state management in stream processing Joy Banerjee 2017-06-13
7484079 Pipeline stage initialization via task frame accessed by a memory pointer propagated among the pipeline stages Mukund Sivaraman 2009-01-27 $20,249,000
7107199 Method and system for the design of pipelines of processors Robert Schreiber, Vinod K. Kathail, Santosh Abraham, Bantwal R. Rau 2006-09-12 $7,515,000
7096438 Method of using clock cycle-time in determining loop schedules during circuit design Mukund Sivaraman 2006-08-22 $15,485,000
7000137 System for and method of clock cycle-time analysis using mode-slicing mechanism Mukund Sivaraman 2006-02-14 $14,109,000
6966043 Method for designing minimal cost, timing correct hardware during circuit synthesis Mukund Sivaraman 2005-11-15 $31,107,000
6952816 Methods and apparatus for digital circuit design generation Bantwal R. Rau, Mukund Sivaraman, Darren C. Conquist, Robert Schreiber, Michael Schlansker 2005-10-04 $19,322,000
6853970 Automatic design of processor datapaths B. Ramakrishna Rau 2005-02-08 $10,023,000
6766445 Storage system for use in custom loop accelerators and the like Michael Schlansker, Vinod K. Kathail 2004-07-20 $10,517,000
6651222 Automatic design of VLIW processors B. Ramakrishna Rau, Vinod K. Kathail, Michael Schlansker 2003-11-18 $9,447,000
6629312 Programmatic synthesis of a machine description for retargeting a compiler 2003-09-30 $13,532,000
6581187 Automatic design of VLIW processors B. Ramakrishna Rau, Vinod K. Kathail, Michael Schlansker 2003-06-17 $19,625,000