Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for designing minimal cost, timing correct hardware during circuit synthesis

Method for designing minimal cost, timing correct hardware during circuit synthesis

US Patent 6966043 · Granted Nov 15, 2005

Estimated economic value: $31,107,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Implementing data flows of an application across a memory hierarchy of a data pr2024
Modeling and compiling tensor processing applications for a computing platform u2024
Control and reconfiguration of data flow graphs on heterogeneous computing platf2023
Hardware-software design flow with high-level synthesis for heterogeneous and pr2023
Implementing an application specified as a data flow graph in an array of data p2022
Control and reconfiguration of data flow graphs on heterogeneous computing platf2022
Dataflow graph programming environment for a heterogenous processing system2021
Hardware-software design flow with high-level synthesis for heterogeneous and pr2021
Constraints for applications in a heterogeneous programming environment2021
Flow convergence during hardware-software design for heterogeneous and programma2021
Hardware-software design flow for heterogeneous and programmable devices2021
Partitioning in a compiler flow for a heterogeneous multi-core architecture2020