Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12159057 | Implementing data flows of an application across a memory hierarchy of a data processing array | Chia-Jui Hsu, Vinod K. Kathail | 2024-12-03 |
| 12135990 | Modeling and compiling tensor processing applications for a computing platform using multi-layer adaptive data flow graphs | Chia-Jui Hsu, Vinod K. Kathail | 2024-11-05 |
| 10860766 | Compilation flow for a heterogeneous multi-core architecture | Shail Aditya Gupta, Akella Sastry, Rishi Surendran, Philip B. James-Roxby, Samuel R. Bayliss +3 more | 2020-12-08 |
| 10628622 | Stream FIFO insertion in a compilation flow for a heterogeneous multi-core architecture | Shail Aditya Gupta, Abnikant Singh | 2020-04-21 |
| 10372858 | Design-for-testability (DFT) insertion at register-transfer-level (RTL) | Eyal Odiz, Janet L. Olson | 2019-08-06 |
| 7484079 | Pipeline stage initialization via task frame accessed by a memory pointer propagated among the pipeline stages | Shail Aditya Gupta | 2009-01-27 |
| 7096438 | Method of using clock cycle-time in determining loop schedules during circuit design | Shail Aditya Gupta | 2006-08-22 |
| 7000137 | System for and method of clock cycle-time analysis using mode-slicing mechanism | Shail Aditya Gupta | 2006-02-14 |
| 6966043 | Method for designing minimal cost, timing correct hardware during circuit synthesis | Shail Aditya Gupta | 2005-11-15 |
| 6952816 | Methods and apparatus for digital circuit design generation | Bantwal R. Rau, Darren C. Conquist, Robert Schreiber, Michael Schlansker, Shail Aditya Gupta | 2005-10-04 |