| 12307217 |
Dynamic adjustment of floating point exponent bias for exponent compression |
Eric F. Dellinger |
2025-05-20 |
|
| 12200087 |
Dynamic data conversion for network computer systems |
Edward J. Richter, Paul M. Hartke |
2025-01-14 |
|
| 11824564 |
Lossless compression using subnormal floating point values |
Eric F. Dellinger |
2023-11-21 |
|
| 11687327 |
Control and reconfiguration of data flow graphs on heterogeneous computing platform |
Chia-Jui Hsu, Shail Aditya Gupta, Samuel R. Bayliss, Ralph D. Wittig, Vinod K. Kathail |
2023-06-27 |
|
| 11573726 |
Data processing engine arrangement in a device |
Juan J. Noguera Serra, Goran H K Bilski, Jan Langer, Baris Ozgul, Richard L. Walke +3 more |
2023-02-07 |
|
| 11281440 |
Control and reconfiguration of data flow graphs on heterogeneous computing platform |
Chia-Jui Hsu, Shail Aditya Gupta, Samuel R. Bayliss, Ralph D. Wittig, Vinod K. Kathail |
2022-03-22 |
|
| 11216275 |
Converting floating point data into integer data using a dynamically adjusted scale factor |
Eric F. Dellinger |
2022-01-04 |
$69,076,000 |
| 11204745 |
Dataflow graph programming environment for a heterogenous processing system |
Shail Aditya Gupta, Samuel R. Bayliss, Vinod K. Kathail, Ralph D. Wittig, Akella Sastry |
2021-12-21 |
$86,928,000 |
| 10990552 |
Streaming interconnect architecture for data processing engine array |
Goran H K Bilski, Peter McColgan, Juan J. Noguera Serra, Baris Ozgul, Jan Langer +4 more |
2021-04-27 |
$39,071,000 |
| 10860766 |
Compilation flow for a heterogeneous multi-core architecture |
Mukund Sivaraman, Shail Aditya Gupta, Akella Sastry, Rishi Surendran, Samuel R. Bayliss +3 more |
2020-12-08 |
$24,793,000 |
| 10802807 |
Control and reconfiguration of data flow graphs on heterogeneous computing platform |
Chia-Jui Hsu, Shail Aditya Gupta, Samuel R. Bayliss, Ralph D. Wittig, Vinod K. Kathail |
2020-10-13 |
$57,700,000 |
| 10747690 |
Device with data processing engine array |
Goran H K Bilski, Juan J. Noguera Serra, Baris Ozgul, Jan Langer, Richard L. Walke +3 more |
2020-08-18 |
$22,481,000 |
| 9846660 |
Heterogeneous multiprocessor platform targeting programmable integrated circuits |
Henry E. Styles, Jeffrey M. Fifield, Ralph D. Wittig, Sonal Santan, Devadas Varma +3 more |
2017-12-19 |
$13,306,000 |
| 9678150 |
Methods and circuits for debugging circuit designs |
Graham F. Schelle, Yi-Hua Edward Yang, Paul R. Schumacher, Patrick Lysaght |
2017-06-13 |
$18,200,000 |
| 9383986 |
Safe low cost web services software deployments |
Jeffrey D. Stroomer, Sean A. Kelly, Raul E. Rangel |
2016-07-05 |
$235,221,000 |
| 9325602 |
Low-risk deployment of web services |
Jeffrey D. Stroomer, Raul E. Rangel |
2016-04-26 |
$140,141,000 |
| 9288252 |
Managing web services using a reverse proxy |
Jeffrey D. Stroomer, Sean A. Kelly, Raul E. Rangel |
2016-03-15 |
$162,435,000 |
| 9218443 |
Heterogeneous multiprocessor program compilation targeting programmable integrated circuits |
Henry E. Styles, Jeffrey M. Fifield, Ralph D. Wittig, Sonal Santan, Devadas Varma +3 more |
2015-12-22 |
$26,461,000 |
| 8595442 |
Redundantly validating values with a processor and a check circuit |
Austin H. Lesea |
2013-11-26 |
$4,683,000 |
| 8479042 |
Transaction-level lockstep |
Ralph D. Wittig |
2013-07-02 |
$9,611,000 |
| 8443230 |
Methods and systems with transaction-level lockstep |
Ralph D. Wittig, Brendan K. Bridgford, Robert M. McGee, Richard DeFelice |
2013-05-14 |
$4,138,000 |
| 8284772 |
Method for scheduling a network packet processor |
Eric R. Keller |
2012-10-09 |
$7,096,000 |
| 8127262 |
Communicating state data between stages of pipelined packet processor |
Michael E. Attig |
2012-02-28 |
$48,236,000 |
| 8122239 |
Method and apparatus for initializing a system configured in a programmable logic device |
Stephen A. Neuendorffer, Henry E. Styles |
2012-02-21 |
$4,864,000 |
| 8065130 |
Method for message processing on a programmable logic device |
Gordon J. Brebner, Eric R. Keller, Chidamber R. Kulkarni |
2011-11-22 |
$4,107,000 |
