Issued Patents All Time
Showing 25 most recent of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12314735 | Data processing array event trace and profiling using processor system executed kernels | Nishant Mysore, Anurag Dubey, Jason Villarreal | 2025-05-27 |
| 12298887 | Data processing array event trace customization, offload, and analysis | Anurag Dubey, Roger Ng, Ishita Ghosh, Scott H. Jonas, Krishnan Subramanian +1 more | 2025-05-13 |
| 11861171 | High-throughput regular expression processing with capture using an integrated circuit | Sachin Kumawat, David K. Liddell | 2024-01-02 |
| 10816600 | Protocol analysis and visualization during simulation | David K. Liddell | 2020-10-27 |
| 10740210 | Kernel tracing for a heterogeneous computing platform and data mining | Kumar Deepak, Roger Ng, David K. Liddell | 2020-08-11 |
| 10713404 | Customizable debug and profile monitoring of reconfigurable systems | Anurag Dubey, Pramod Chandraiah, Stephen P. Rozum, Hem C. Neema | 2020-07-14 |
| 10380313 | Implementation and evaluation of designs for heterogeneous computing platforms with hardware acceleration | Kumar Deepak, Scott H. Jonas | 2019-08-13 |
| 10282326 | Active interrupt handler performance monitoring in microprocessors | Yi-Hua Edward Yang, Patrick Lysaght, Austin H. Lesea, Graham F. Schelle | 2019-05-07 |
| 9977758 | Device profiling for tuning OpenCL applications on programmable integrated circuits | Kumar Deepak, Graham F. Schelle | 2018-05-22 |
| 9846587 | Performance analysis using configurable hardware emulation within an integrated circuit | Graham F. Schelle, Patrick Lysaght, Yi-Hua Edward Yang | 2017-12-19 |
| 9846449 | System and method for monitoring bus transactions within a programmable integrated circuit by selectively inserting detector circuit at user specified insertion point corresponding to a bus interconnect | Graham F. Schelle, Bradley K. Fross | 2017-12-19 |
| 9678150 | Methods and circuits for debugging circuit designs | Graham F. Schelle, Yi-Hua Edward Yang, Philip B. James-Roxby, Patrick Lysaght | 2017-06-13 |
| 9665683 | Designing a system for a programmable system-on-chip using performance characterization techniques | Graham F. Schelle, Patrick Lysaght | 2017-05-30 |
| 9652410 | Automated modification of configuration settings of an integrated circuit | Graham F. Schelle, Patrick Lysaght, Yi-Hua Edward Yang, Anthony W. Brandon | 2017-05-16 |
| 9639646 | System-on-chip intellectual property block discovery | Graham F. Schelle, Adrian M. Hernandez | 2017-05-02 |
| 9626780 | Visualizing transactions of a transaction-based system | Yi-Hua Edward Yang, Patrick Lysaght, Graham F. Schelle | 2017-04-18 |
| 9608871 | Intellectual property cores with traffic scenario data | Graham F. Schelle | 2017-03-28 |
| 9581643 | Methods and circuits for testing partial circuit designs | Graham F. Schelle, Yi-Hua Edward Yang, Patrick Lysaght | 2017-02-28 |
| 9529946 | Performance estimation using configurable hardware emulation | Graham F. Schelle, Patrick Lysaght, Alan M. Frost | 2016-12-27 |
| 9348619 | Interactive datasheet system | Patrick Lysaght, Graham F. Schelle, Yi-Hua Edward Yang | 2016-05-24 |
| 9323876 | Integrated circuit pre-boot metadata transfer | Patrick Lysaght, Yi-Hua Edward Yang, Graham F. Schelle | 2016-04-26 |
| 9117046 | Method of generating data for estimating resource requirements for a circuit design | Ian Miller, David B. Parlour, Jorn W. Janneck, Pradip K. Jha | 2015-08-25 |
| 9081925 | Estimating system performance using an integrated circuit | Graham F. Schelle, Patrick Lysaght | 2015-07-14 |
| 9058135 | Synchronization of timers across clock domains in a digital system | Graham F. Schelle | 2015-06-16 |
| 8495538 | Power estimation of a circuit design | Alan M. Frost, Timothy J. Burke | 2013-07-23 |