Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11836426 | Early detection of sequential access violations for high level synthesis | Fangqing Du, Alexandre Isoard, Lin-Ya Yu | 2023-12-05 |
| 11762762 | Static and automatic inference of inter-basic block burst transfers for high-level synthesis | Lin-Ya Yu, Alexandre Isoard | 2023-09-19 |
| 11720422 | Unified container for hardware and software binaries | Sonal Santan, Soren T. Soe, Stephen P. Rozum, Nik Cimino | 2023-08-08 |
| 11474555 | Data-driven platform characteristics capture and discovery for hardware accelerators | Sonal Santan, Julian M. Kain, Stephen P. Rozum, Khang K. Dao, Kyle Corbett | 2022-10-18 |
| 11314911 | High-level synthesis implementation of data structures in hardware | Fangqing Du, Sheng Wang, Alain Darte, Alexandre Isoard, Lin-Ya Yu | 2022-04-26 |
| 11238199 | High-level synthesis vector library for single-instruction multiple data programming and electronic system design | Alexandre Isoard, Lin-Ya Yu | 2022-02-01 |
| 11042610 | Enabling integrity and authenticity of design data | Sonal Santan, Bin Ochotta | 2021-06-22 |
| 10956241 | Unified container for hardware and software binaries | Sonal Santan, Soren T. Soe, Stephen P. Rozum, Nik Cimino | 2021-03-23 |
| 10924430 | Streaming platform flow and architecture for an integrated circuit | Chandrasekhar S. Thyamagondlu, Kenneth K. Chan, Ravi N. Kurlagunda, Karen Xie, Sonal Santan +1 more | 2021-02-16 |
| 10922068 | Updating firmware for programmable integrated circuits in computing environments | Ryan RADJABI, Sonal Santan, Yenpang Lin | 2021-02-16 |
| 10877766 | Embedded scheduling of hardware resources for hardware acceleration | Soren T. Soe, Idris I. Tarwala, Umang Parekh, Sonal Santan | 2020-12-29 |
| 10802995 | Unified address space for multiple hardware accelerators using dedicated low latency links | Sarabjeet Singh, Sonal Santan, Khang K. Dao, Kyle Corbett, Yi-Fan Wang +1 more | 2020-10-13 |
| 10713404 | Customizable debug and profile monitoring of reconfigurable systems | Paul R. Schumacher, Anurag Dubey, Pramod Chandraiah, Stephen P. Rozum | 2020-07-14 |
| 10642811 | Address-based waveform database architecture | David K. Liddell, Roger Ng | 2020-05-05 |
| 10296673 | Mixed-language simulation | Ishita Ghosh, Jason Villarreal, Saikat Bandyopadhyay, Kumar Deepak | 2019-05-21 |
| 9223910 | Performance and memory efficient modeling of HDL ports for simulation | Ishita Ghosh, Saikat Bandyopadhyay, Kumar Deepak, David K. Liddell | 2015-12-29 |
| 9135384 | Compilation and simulation of a circuit design | Sonal Santan, Valeria Mihalache | 2015-09-15 |
| 9117043 | Net sensitivity ranges for detection of simulation events | Lixin Huang, Sonal Santan | 2015-08-25 |
| 8868396 | Verification and debugging using heterogeneous simulation models | Nabeel Shirazi, L. James Hwang, Chi Bun Chan, Kumar Deepak | 2014-10-21 |
| 8838431 | Mixed-language simulation | Valeria Mihalache, Kumar Deepak, Sonal Santan | 2014-09-16 |
| 8516413 | Compilation and simulation of a circuit design | Sandeep S. Deshpande, Valeria Mihalache, Kumar Deepak, Sonal Santan, David K. Liddell | 2013-08-20 |
| 8495539 | Scheduling processes in simulation of a circuit design | Valeria Mihalache, Kumar Deepak, Sonal Santan | 2013-07-23 |
| 8447581 | Generating simulation code from a specification of a circuit design | David Roth | 2013-05-21 |
| 8418095 | Compilation and simulation of a circuit design | Sonal Santan, Kumar Deepak | 2013-04-09 |
| 8327311 | Generating a simulation model of a circuit design | Sonal Santan, Kumar Deepak | 2012-12-04 |