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Variable buffer size descriptor fetching for a multi-queue direct memory access system |
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Direct memory access system with read reassembly circuit |
Nicholas Trank |
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Data bus width configurable interconnection circuitry |
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Firewalling communication ports in a multi-port system |
Akhil Krishnan, Darren S. Jue |
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Descriptor cache eviction for multi-queue direct memory access |
Tao Yu |
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Descriptor fetching for a multi-queue direct memory access system |
Tao Yu, Chiranjeevi Sirandas, Nicholas Trank |
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Multi-host direct memory access system for integrated circuits |
Darren S. Jue, Ravi Sunkavalli, Akhil Krishnan, Tao Yu, Kushagra Sharma |
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Chuan Cheng Pan, Hanh Hoang |
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Multi-host direct memory access system for integrated circuits |
Darren S. Jue, Ravi Sunkavalli, Akhil Krishnan, Tao Yu, Kushagra Sharma |
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Ellery Cochell, Brian S. Martin, Ravi N. Kurlagunda |
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Dynamically reconfigurable networking using a programmable integrated circuit |
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Customizable multi queue DMA interface |
Darren S. Jue, Tao Yu, John West, Hanh Hoang, Ravi Sunkavalli |
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Streaming platform architecture for inter-kernel circuit communication for an integrated circuit |
Ravi N. Kurlagunda, Kenneth K. Chan, Ravi Sunkavalli |
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Interrupt moderation and aggregation circuitry |
Darren S. Jue, Tao Yu, Kushagra Sharma, Tuan Van-Dinh |
2020-05-19 |