Issued Patents All Time
Showing 25 most recent of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11726936 | Multi-host direct memory access system for integrated circuits | Chandrasekhar S. Thyamagondlu, Darren S. Jue, Akhil Krishnan, Tao Yu, Kushagra Sharma | 2023-08-15 |
| 11232053 | Multi-host direct memory access system for integrated circuits | Chandrasekhar S. Thyamagondlu, Darren S. Jue, Akhil Krishnan, Tao Yu, Kushagra Sharma | 2022-01-25 |
| 11194490 | Data formatter for convolution | Victor J. Wu, Poching Sun | 2021-12-07 |
| 10990547 | Dynamically reconfigurable networking using a programmable integrated circuit | Chandrasekhar S. Thyamagondlu, Ravi N. Kurlagunda, Ellery Cochell | 2021-04-27 |
| 10983920 | Customizable multi queue DMA interface | Chandrasekhar S. Thyamagondlu, Darren S. Jue, Tao Yu, John West, Hanh Hoang | 2021-04-20 |
| 10725942 | Streaming platform architecture for inter-kernel circuit communication for an integrated circuit | Chandrasekhar S. Thyamagondlu, Ravi N. Kurlagunda, Kenneth K. Chan | 2020-07-28 |
| 10659437 | Cryptographic system | Anujan Varma, Chuan Cheng Pan, Patrick C. McCarthy, Hanh Hoang | 2020-05-19 |
| 9455036 | System architectures with data transfer paths between different memory types | Ed McKernan, Malcolm Wing | 2016-09-27 |
| 9443584 | Network interface with logging | Malcolm Wing | 2016-09-13 |
| 9208870 | Multi-port memory devices and methods having programmable impedance elements | — | 2015-12-08 |
| 9147464 | System architecture with multiple memory types, including programmable impedance memory elements | Ed McKernan, Malcolm Wing | 2015-09-29 |
| 9047975 | Coding techniques for reducing write cycles for memory | Malcolm Wing | 2015-06-02 |
| 8982602 | Memory devices, circuits and, methods that apply different electrical conditions in access operations | Malcolm Wing | 2015-03-17 |
| 8933734 | Hierarchical global clock tree | Rahul Nimaiyar, Ravi N. Kurlagunda, Vijay Bantval | 2015-01-13 |
| 8902631 | Memory devices, circuits and, methods that apply different electrical conditions in access operations | Ishai Naveh, Malcolm Wing | 2014-12-02 |
| 8700837 | System and method of signal processing engines with programmable logic fabric | Hare K. Verma, Manoj Gunwani | 2014-04-15 |
| 8638138 | Hierarchical global clock tree | Rahul Nimaiyar, Ravi N. Kurlagunda, Vijay Bantval | 2014-01-28 |
| 8429214 | Programmable logic systems and methods employing configurable floating point units | Hare K. Verma, Manoj Gunwani | 2013-04-23 |
| 8305124 | Reset signal distribution | Ravi N. Kurlagunda, Vijay Bantval, Rahul Nimaiyar | 2012-11-06 |
| 8228101 | Source-synchronous clocking | Rahul Nimaiyar | 2012-07-24 |
| 8131909 | System and method of signal processing engines with programmable logic fabric | Hare K. Verma, Manoj Gunwani | 2012-03-06 |
| 8072250 | Reset signal distribution | Ravi N. Kurlagunda, Vijay Bantval, Rahul Nimaiyar | 2011-12-06 |
| 7970979 | System and method of configurable bus-based dedicated connection circuits | Hare K. Verma, Manoj Gunwani | 2011-06-28 |
| 7836113 | Dedicated logic cells employing configurable logic and dedicated logic functions | Hare K. Verma, Manoj Gunwani, Elliott Delaye | 2010-11-16 |
| 7814136 | Programmable logic systems and methods employing configurable floating point units | Hare K. Verma, Manoj Gunwani | 2010-10-12 |