| 12511460 |
Hardware acceleration of machine learning designs |
Ehsan Ghasemi, Rajeev Patwari, Jorn Tuyls, Ephrem C. Wu, Xiao Teng +1 more |
2025-12-30 |
|
| 12248786 |
Instruction set architecture for data processing array control |
Xiao Teng, Tejus Siddagangaiah, Bryan Lozano, Ehsan Ghasemi, Rajeev Patwari +5 more |
2025-03-11 |
|
| 12147379 |
Scalable acceleration of reentrant compute operations |
Rajeev Patwari, Jorn Tuyls, Xiao Teng, Ephrem C. Wu |
2024-11-19 |
|
| 12086572 |
Software defined neural network layer pipelining |
Yongjun Wu, Jindrich Zejda, Ashish Sirasao |
2024-09-10 |
|
| 12079158 |
Reconfigurable neural engine with extensible instruction set architecture |
Sanket Pandit, Jorn Tuyls, Xiao Teng, Rajeev Patwari, Ehsan Ghasemi +1 more |
2024-09-03 |
|
| 12061990 |
Static block scheduling in massively parallel software defined hardware systems |
Yongjun Wu, Jindrich Zejda, Ashish Sirasao |
2024-08-13 |
|
| 11694066 |
Machine learning runtime library for neural network acceleration |
Aaron Ng, Jindrich Zejda, Xiao Teng, Sonal Santan, Soren T. Soe +3 more |
2023-07-04 |
|
| 11620490 |
Multi-layer neural network processing by a neural network accelerator using host communicated merged weights and a package of per-layer instructions |
Aaron Ng, Ehsan Ghasemi, Xiao Teng, Jindrich Zejda, Yongjun Wu +2 more |
2023-04-04 |
|
| 11568218 |
Neural network processing system having host controlled kernel acclerators |
Aaron Ng, Jindrich Zejda, Xiao Teng, Ashish Sirasao |
2023-01-31 |
|
| 11429848 |
Host-directed multi-layer neural network processing via per-layer work requests |
Aaron Ng, Jindrich Zejda, Ashish Sirasao |
2022-08-30 |
|
| 11386644 |
Image preprocessing for generalized image processing |
Ashish Sirasao, Aaron Ng, Yongjun Wu, Jindrich Zejda |
2022-07-12 |
|
| 11222256 |
Neural network processing system having multiple processors and a neural network accelerator |
Xiao Teng, Aaron Ng, Ashish Sirasao |
2022-01-11 |
$194,948,000 |
| 11204747 |
Re-targetable interface for data exchange between heterogeneous systems and accelerator abstraction into software instructions |
Jindrich Zejda, Yongjun Wu, Aaron Ng, Ashish Sirasao, Khang K. Dao +1 more |
2021-12-21 |
$86,928,000 |
| 11106968 |
Circuit arrangements and methods for traversing input feature maps |
Ehsan Ghasemi, Ashish Sirasao |
2021-08-31 |
$32,901,000 |
| 11036827 |
Software-defined buffer/transposer for general matrix multiplication in a programmable IC |
Jindrich Zejda, Yongjun Wu, Aaron Ng, Ashish Sirasao, Khang K. Dao |
2021-06-15 |
$93,994,000 |
| 10984500 |
Inline image preprocessing for convolution operations using a matrix multiplier on an integrated circuit |
Ashish Sirasao, Aaron Ng, Ehsan Ghasemi |
2021-04-20 |
$84,827,000 |
| 10943039 |
Software-driven design optimization for fixed-point multiply-accumulate circuitry |
Ashish Sirasao, Sean Settle, Zhao Ma, Ehsan Ghasemi, Xiao Teng +2 more |
2021-03-09 |
$44,926,000 |
| 10678509 |
Software-driven design optimization for mapping between floating-point and fixed-point multiply accumulators |
Sean Settle, Aaron Ng, Ehsan Ghasemi, Ashish Sirasao, Xiao Teng +1 more |
2020-06-09 |
$35,785,000 |
| 10572225 |
Circuit arrangements and methods for performing multiply-and-accumulate operations |
Ehsan Ghasemi, Ashish Sirasao, Sean Settle |
2020-02-25 |
$24,408,000 |
| 10515135 |
Data format suitable for fast massively parallel general matrix multiplication in a programmable IC |
Jindrich Zejda, Aaron Ng, Ashish Sirasao, Yongjun Wu |
2019-12-24 |
$107,121,000 |
| 10460416 |
Inline image preprocessing for convolution operations using a matrix multiplier on an integrated circuit |
Ashish Sirasao, Aaron Ng, Ehsan Ghasemi |
2019-10-29 |
$199,342,000 |
| 10411709 |
Circuit arrangements and methods for dividing a three-dimensional input feature map |
Ehsan Ghasemi, Ashish Sirasao |
2019-09-10 |
$48,855,000 |
| 10354733 |
Software-defined memory bandwidth reduction by hierarchical stream buffering for general matrix multiplication in a programmable IC |
Jindrich Zejda, Ashish Sirasao, Yongjun Wu, Aaron Ng |
2019-07-16 |
$293,557,000 |
| 10303833 |
Parallelizing timing-based operations for circuit designs |
Aman Gayasen, Surya Pratik Saha, Shangzhi Sun, Ashish Sirasao |
2019-05-28 |
$41,882,000 |
| 9460253 |
Selecting predefined circuit implementations in a circuit design system |
Ashish Sirasao, Krishna Garlapati, Bing Tian |
2016-10-04 |
$14,677,000 |
