Issued Patents All Time
Showing 25 most recent of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12086572 | Software defined neural network layer pipelining | Yongjun Wu, Jindrich Zejda, Elliott Delaye | 2024-09-10 |
| 12061990 | Static block scheduling in massively parallel software defined hardware systems | Yongjun Wu, Jindrich Zejda, Elliott Delaye | 2024-08-13 |
| 11694066 | Machine learning runtime library for neural network acceleration | Aaron Ng, Jindrich Zejda, Elliott Delaye, Xiao Teng, Sonal Santan +3 more | 2023-07-04 |
| 11620490 | Multi-layer neural network processing by a neural network accelerator using host communicated merged weights and a package of per-layer instructions | Aaron Ng, Elliott Delaye, Ehsan Ghasemi, Xiao Teng, Jindrich Zejda +2 more | 2023-04-04 |
| 11568218 | Neural network processing system having host controlled kernel acclerators | Aaron Ng, Jindrich Zejda, Elliott Delaye, Xiao Teng | 2023-01-31 |
| 11449347 | Time-multiplexed implementation of hardware accelerated functions in a programmable integrated circuit | Raymond Kong, Brian S. Martin, Hao Yu, Jun Liu | 2022-09-20 |
| 11429848 | Host-directed multi-layer neural network processing via per-layer work requests | Aaron Ng, Elliott Delaye, Jindrich Zejda | 2022-08-30 |
| 11386644 | Image preprocessing for generalized image processing | Elliott Delaye, Aaron Ng, Yongjun Wu, Jindrich Zejda | 2022-07-12 |
| 11222256 | Neural network processing system having multiple processors and a neural network accelerator | Xiao Teng, Aaron Ng, Elliott Delaye | 2022-01-11 |
| 11204747 | Re-targetable interface for data exchange between heterogeneous systems and accelerator abstraction into software instructions | Jindrich Zejda, Elliott Delaye, Yongjun Wu, Aaron Ng, Khang K. Dao +1 more | 2021-12-21 |
| 11188697 | On-chip memory access pattern detection for power and resource reduction | Chaithanya Dudha, Rajeev Patwari, Nithin Kumar Guggilla, Krishna Garlapati | 2021-11-30 |
| 11106968 | Circuit arrangements and methods for traversing input feature maps | Ehsan Ghasemi, Elliott Delaye | 2021-08-31 |
| 11036827 | Software-defined buffer/transposer for general matrix multiplication in a programmable IC | Jindrich Zejda, Elliott Delaye, Yongjun Wu, Aaron Ng, Khang K. Dao | 2021-06-15 |
| 10990736 | Implementing a circuit design with re-convergence | Chaithanya Dudha, Satyaprakash Pareek, Krishna Garlapati | 2021-04-27 |
| 10990826 | Object detection in video | Mujib Haider, Venkata V. Dhanikonda | 2021-04-27 |
| 10984500 | Inline image preprocessing for convolution operations using a matrix multiplier on an integrated circuit | Elliott Delaye, Aaron Ng, Ehsan Ghasemi | 2021-04-20 |
| 10943039 | Software-driven design optimization for fixed-point multiply-accumulate circuitry | Elliott Delaye, Sean Settle, Zhao Ma, Ehsan Ghasemi, Xiao Teng +2 more | 2021-03-09 |
| 10936311 | Sparse matrix processing circuitry | Ling Liu, Yifei Zhou, Xiao Teng, Chuanhua Song, Aaron Ng | 2021-03-02 |
| 10824434 | Dynamically structured single instruction, multiple data (SIMD) instructions | Sean Settle, Ehsan Ghasemi, Ralph D. Wittig | 2020-11-03 |
| 10747502 | Multiply and accumulate circuit | Satyaprakash Pareek, Anup Hosangadi, Bing Tian, Yao Fu, Oscar Fernando C. Fernandez +2 more | 2020-08-18 |
| 10726175 | Systems for optimization of read-only memory (ROM) | Chaithanya Dudha, Satyaprakash Pareek, Bing Tian | 2020-07-28 |
| 10678509 | Software-driven design optimization for mapping between floating-point and fixed-point multiply accumulators | Sean Settle, Elliott Delaye, Aaron Ng, Ehsan Ghasemi, Xiao Teng +1 more | 2020-06-09 |
| 10678983 | Local retiming optimization for circuit designs | Shangzhi Sun, Chaithanya Dudha, Bing Tian | 2020-06-09 |
| 10572409 | Sparse matrix processing circuitry | Jindrich Zejda, Ling Liu, Yifei Zhou | 2020-02-25 |
| 10572225 | Circuit arrangements and methods for performing multiply-and-accumulate operations | Ehsan Ghasemi, Elliott Delaye, Sean Settle | 2020-02-25 |