Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11842168 | Circuit architecture for determining threshold ranges and values of a dataset | Sai Lalith Chaitanya Ambatipudi, Vamsi Nalluri, Sandeep Jayant Sathe, Krishna Kishore Bhagavatula | 2023-12-12 |
| 11429769 | Implementing a hardware description language memory using heterogeneous memory primitives | Pradip Kar, Nithin Kumar Guggilla, Satyaprakash Pareek | 2022-08-30 |
| 11188697 | On-chip memory access pattern detection for power and resource reduction | Rajeev Patwari, Nithin Kumar Guggilla, Ashish Sirasao, Krishna Garlapati | 2021-11-30 |
| 11100267 | Multi dimensional memory compression using bytewide write enable | Nithin Kumar Guggilla, Pradip Kar | 2021-08-24 |
| 10990736 | Implementing a circuit design with re-convergence | Satyaprakash Pareek, Krishna Garlapati, Ashish Sirasao | 2021-04-27 |
| 10726175 | Systems for optimization of read-only memory (ROM) | Satyaprakash Pareek, Bing Tian, Ashish Sirasao | 2020-07-28 |
| 10678983 | Local retiming optimization for circuit designs | Shangzhi Sun, Bing Tian, Ashish Sirasao | 2020-06-09 |
| 10642951 | Register pull-out for sequential circuit blocks in circuit designs | Govinda Keshavdas, Anup Kumar Sultania, Sabyasachi Das | 2020-05-05 |
| 10606979 | Verifying equivalence of design latency | Shangzhi Sun, Bing Tian | 2020-03-31 |
| 10430539 | Method and apparatus for enhancing performance by moving or adding a pipelined register stage in a cascaded chain | Zhao Ma, Krishna Garlapati, Ashish Sirasao | 2019-10-01 |
| 10387600 | Dynamic power reduction in circuit designs and circuits | Krishna Garlapati | 2019-08-20 |
| 10366001 | Partitioning memory blocks for reducing dynamic power consumption | Nithin Kumar Guggilla, Krishna Garlapati, Chun Zhang, Fan Zhang, Anup Kumar Sultania | 2019-07-30 |
| 10289786 | Circuit design transformation for automatic latency reduction | Shangzhi Sun, Ashish Sirasao, Nithin Kumar Guggilla | 2019-05-14 |