| 11947885 |
Low-power static signoff verification from within an implementation tool |
Meera Viswanath, David L. Allen, Kaushik De, Renu Mehra, Godwin R. Maben |
2024-04-02 |
$133,460,000 |
| 11449660 |
Method to perform secondary-PG aware buffering in IC design flow |
Jin-Mu Wu, Renu Mehra, Ben Mathew, Kunming Ho |
2022-09-20 |
$154,394,000 |
| 10970446 |
Automated pipeline insertion on a bus |
Jeffrey H. Seltzer, Khang K. Dao |
2021-04-06 |
|
| 10839125 |
Post-placement and post-routing physical synthesis for multi-die integrated circuits |
Sreesan Venkatakrishnan, Ruibing Lu |
2020-11-17 |
$30,681,000 |
| 10699053 |
Timing optimization of memory blocks in a programmable IC |
Zhiyong Wang, Ruibing Lu, Lin CHAI |
2020-06-30 |
$33,305,000 |
| 10642951 |
Register pull-out for sequential circuit blocks in circuit designs |
Govinda Keshavdas, Anup Kumar Sultania, Chaithanya Dudha |
2020-05-05 |
$31,719,000 |
| 10572621 |
Physical synthesis within placement |
Zhiyong Wang |
2020-02-25 |
$24,408,000 |
| 10565334 |
Targeted delay optimization through programmable clock delays |
Ruibing Lu |
2020-02-18 |
$44,383,000 |
| 10540463 |
Placement of delay circuits for avoiding hold violations |
Maheshwar Chandrasekar |
2020-01-21 |
$74,241,000 |
| 10528697 |
Timing-closure methodology involving clock network in hardware designs |
Wei-Chun Chen, Xiaojian Yang |
2020-01-07 |
$31,713,000 |
| 10496777 |
Physical synthesis for multi-die integrated circuit technology |
Sreesan Venkatakrishnan, Zhiyong Wang |
2019-12-03 |
$49,935,000 |
| 10303648 |
Logical and physical optimizations for partial reconfiguration design flow |
Zhiyong Wang, Niyati Shah |
2019-05-28 |
$41,882,000 |
| 10242150 |
Circuit design implementation using control-set based merging and module-based replication |
Xiaojian Yang, Niyati Shah, Govinda Keshavdas, Frederic Revenu |
2019-03-26 |
$84,655,000 |
| 10192016 |
Neural network based physical synthesis for circuit designs |
Aaron Ng, Prabal Basu |
2019-01-29 |
$110,280,000 |
| 10068045 |
Programmable logic device design implementations with multiplexer transformations |
Chiwei Huang |
2018-09-04 |
$10,946,000 |
| 9965581 |
Fanout optimization to facilitate timing improvement in circuit designs |
Aaron Ng, Ruibing Lu, Niyati Shah, Zhiyong Wang |
2018-05-08 |
$22,720,000 |
| 9836568 |
Programmable integrated circuit design flow using timing-driven pipeline analysis |
Ilya K. Ganusov, Aaron Ng, Ronald E. Plyler, Frederic Revenu |
2017-12-05 |
$44,047,000 |
| 9773083 |
Post-placement and pre-routing processing of critical paths in a circuit design |
Zhiyong Wang |
2017-09-26 |
$16,957,000 |
| 9767247 |
Look-up table restructuring for timing closure in circuit designs |
Ruibing Lu |
2017-09-19 |
$82,042,000 |
| 9646126 |
Post-routing structural netlist optimization for circuit designs |
Ruibing Lu, Zhiyong Wang, Aaron Ng |
2017-05-09 |
$34,444,000 |
| 9613173 |
Interactive multi-step physical synthesis |
Rajat Aggarwal, Zhiyong Wang, Ruibing Lu |
2017-04-04 |
$28,466,000 |
| 9483597 |
Opportunistic candidate path selection during physical optimization of a circuit design for an IC |
Ruibing Lu, Zhiyong Wang |
2016-11-01 |
$14,332,000 |
| 9235660 |
Selective addition of clock buffers to a circuit design |
Ruibing Lu, Zhiyong Wang |
2016-01-12 |
$4,795,000 |
| 9043735 |
Synthesis of fast squarer functional blocks |
Jean-Charles Giomi |
2015-05-26 |
$5,843,000 |
| 8996943 |
Voltage regulator with by-pass capability for test purposes |
Nicolas Bernard Grossier, V Srinivasan |
2015-03-31 |
$2,314,000 |
