SD

Sabyasachi Das

AM AMD: 21 patents #507 of 9,279Top 6%
CS Cadence Design Systems: 4 patents #399 of 2,263Top 20%
SY Synopsys: 2 patents #669 of 2,302Top 30%
SS Stmicroelectronics Sa: 1 patents #2,729 of 4,662Top 60%
SN Stmicroelectronics International N.V.: 1 patents #346 of 696Top 50%
UC University of Colorado: 1 patents #288 of 930Top 35%
XL Xlnx: 1 patents #1 of 20Top 5%
IN Intel: 1 patents #18,218 of 30,777Top 60%
📍 San Jose, CA: #2,017 of 32,062 inventorsTop 7%
🗺 California: #17,156 of 386,348 inventorsTop 5%
Overall (All Time): #122,915 of 4,157,543Top 3%
30
Patents All Time

Issued Patents All Time

Showing 26–30 of 30 patents

Patent #TitleCo-InventorsDate
8984462 Physical optimization for timing closure for an integrated circuit Ruibing Lu, Zhiyong Wang, Aman Gayasen 2015-03-17
8707225 Synthesis of area-efficient subtractor and divider functional blocks 2014-04-22
8407277 Full subtractor cell for synthesis of area-efficient subtractor and divider 2013-03-26
7739324 Timing driven synthesis of sum-of-product functional blocks Jean-Charles Giomi 2010-06-15
6598215 Datapath design methodology and routing apparatus Sunil Khatri 2003-07-22