Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11829733 | Synthesis flow for data processing engine array applications relying on hardware library packages | Sumanta Datta, Srijan Tiwary | 2023-11-28 |
| 11768663 | Compaction of multiplier and adder circuits | Srijan Tiwary | 2023-09-26 |
| 11755801 | Data flow graph refinement using range set information for improved synthesis | Kishore Vedavyasan, Sumanta Datta, Sriram Govindarajan | 2023-09-12 |
| 11586791 | Visualization of data buses in circuit designs | Anup Hosangadi, Srinivasan Dasasathyan, Padmini Gopalakrishnan | 2023-02-21 |
| 10943042 | Data flow graph optimization techniques for RTL loops with conditional-exit statements | Sumanta Datta | 2021-03-09 |
| 10839118 | Optimization-aware incremental synthesis | Kameshwar Chandrasekar, Manpreet Singh, Surya Pratik Saha, Sanjay Saha | 2020-11-17 |
| 10789401 | Folding multiply-and-accumulate logic | Srijan Tiwary, Kumar S. S. Vemuri | 2020-09-29 |
| 10586005 | Incremental synthesis for changes to a circuit design | Kameshwar Chandrasekar, Surya Pratik Saha, Sumanta Datta | 2020-03-10 |
| 10534885 | Modifying data flow graphs using range information | Sumanta Datta, Anup Hosangadi | 2020-01-14 |
| 10331836 | Loop optimization for implementing circuit designs in hardware | Anup Hosangadi, Sumanta Datta, Ashish Sirasao | 2019-06-25 |
| 10303833 | Parallelizing timing-based operations for circuit designs | Surya Pratik Saha, Elliott Delaye, Shangzhi Sun, Ashish Sirasao | 2019-05-28 |
| 8984462 | Physical optimization for timing closure for an integrated circuit | Sabyasachi Das, Ruibing Lu, Zhiyong Wang | 2015-03-17 |