Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11714950 | Automated timing closure on circuit designs | Veeresh Pratap Singh, Meghraj Kalase, John Blaine, Srinivasan Dasasathyan, Frederic Revenu +4 more | 2023-08-01 |
| 11586791 | Visualization of data buses in circuit designs | Anup Hosangadi, Aman Gayasen, Srinivasan Dasasathyan | 2023-02-21 |
| 11003826 | Automated analysis and optimization of circuit designs | Srinivasan Dasasathyan, Vishal Tripathy, Vikas N. Vedamurthy, Sumit Nagpal | 2021-05-11 |
| 10867093 | System and method for an electronic design tool providing automated guidance and interface for circuit design processing | John Blaine, Srinivasan Dasasathyan, Meghraj Kalase, Frederic Revenu, Veeresh Pratap Singh +4 more | 2020-12-15 |
| 6775808 | Method and apparatus for generating sign-off prototypes for the design and fabrication of integrated circuits | Salil Ravindra Raje, Lawrence Pileggi, Dinesh D. Gaitonde, Olivier Coudert, Jackson David Kreiter | 2004-08-10 |
| 6523161 | Method to optimize net lists using simultaneous placement and logic optimization | Salil Ravindra Raje | 2003-02-18 |