Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12019964 | Optimizing use of computer resources in implementing circuit designs through machine learning | Karthic P, Paul D. Kundarewich, Satish B. Sivaswamy, Vishal Tripathi, Srinivasan Dasasathyan +3 more | 2024-06-25 |
| 11714950 | Automated timing closure on circuit designs | Veeresh Pratap Singh, John Blaine, Srinivasan Dasasathyan, Padmini Gopalakrishnan, Frederic Revenu +4 more | 2023-08-01 |
| 10867093 | System and method for an electronic design tool providing automated guidance and interface for circuit design processing | John Blaine, Srinivasan Dasasathyan, Frederic Revenu, Veeresh Pratap Singh, Satish Bachina +4 more | 2020-12-15 |