| 12327077 |
Deadlock detection and prevention for routing packet-switched nets in electronic systems |
Sreesan Venkatakrishnan, Nitin Deshmukh |
2025-06-10 |
| 12019964 |
Optimizing use of computer resources in implementing circuit designs through machine learning |
Karthic P, Paul D. Kundarewich, Meghraj Kalase, Vishal Tripathi, Srinivasan Dasasathyan +3 more |
2024-06-25 |
| 11875100 |
Distributed parallel processing routing |
Ashot Shakhkyan, Nitin Deshmukh, Garik Mkrtchyan, Guenter Stenz, Bhasker Pinninti |
2024-01-16 |
| 11790139 |
Predicting a performance metric based on features of a circuit design and explaining marginal contributions of the features to the prediction |
Garik Mkrtchyan |
2023-10-17 |
| 11733980 |
Application implementation and buffer allocation for a data processing engine array |
Brian Guttag, Nitin Deshmukh |
2023-08-22 |
| 11709521 |
Synchronous clock domain crossing skew optimization and multi-clock buffer (MBUFG) |
Frederic Revenu, Frank Mueller, Thomas O. Satter, Mehrdad Eslami Dehkordi, Garik Mkrtchyan +2 more |
2023-07-25 |
| 11604751 |
Optimizing hardware design throughput by latency aware balancing of re-convergent paths |
Brian Guttag, Nitin Deshmukh, Sreesan Venkatakrishnan |
2023-03-14 |
| 11238206 |
Partition wire assignment for routing multi-partition circuit designs |
Nitin Deshmukh, Garik Mkrtchyan, Grigor S. Gasparyan |
2022-02-01 |
| 11108644 |
Data processing engine (DPE) array routing |
Garik Mkrtchyan, Jinny Singh |
2021-08-31 |
| 10318699 |
Fixing hold time violations using hold time budgets and slacks of setup times |
Parivallal Kannan |
2019-06-11 |
| 9842187 |
Representation of complex timing characteristics of startpoint-endpoint pairs in a circuit design |
Jindrich Zejda, Atul Srinivasan, Ilya K. Ganusov, Walter A. Manaker, Jr., Benjamin S. Devlin |
2017-12-12 |