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Fast interference graph construction for a binary tree of interval nodes |
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Micro-network-on-chip and microsector infrastructure |
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Balanced partitioning of neural network based on execution latencies |
Fabio Nonato de Paula, Preston Pengra Briggs, III |
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Timing optimizations in circuit designs using opposite clock edge triggered flip-flops |
Guenter Stenz |
2019-09-17 |
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Fixing hold time violations using hold time budgets and slacks of setup times |
Satish B. Sivaswamy |
2019-06-11 |
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Signal routing and pin placement |
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2012-06-05 |
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Congestion elimination using adaptive cost schedule to route signals within an integrated circuit |
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2012-02-21 |
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Assignment of select input/output blocks to banks for integrated circuits using integer linear programming with proximity optimization |
Victor Z. Slonim, Guenter Stenz |
2011-08-30 |
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Placement of I/O blocks within I/O banks using an integer linear programming formulation |
Victor Z. Slonim, Guenter Stenz |
2011-06-07 |
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Recursive partitioning based placement for programmable logic devices using non-rectilinear device-cutlines |
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2009-05-05 |
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Skew-driven routing for networks |
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2009-04-07 |
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Assignment of select I/O objects to banks with mixed capacities using integer linear programming |
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2009-01-20 |
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Simultaneous assignment of select I/O objects and clock I/O objects to banks using integer linear programming |
Victor Z. Slonim, Salim Abid |
2008-11-11 |
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Method of flexible clock placement for integrated circuit designs using integer linear programming |
Victor Z. Slonim, Salim Abid |
2008-04-01 |