Issued Patents All Time
Showing 25 most recent of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12425030 | Systems and methods for configurable interface circuits | Paul Rotker, Lai Guan Tang, Luis Hau | 2025-09-23 |
| 12411174 | Circuits and methods for configurable scan chains | Bee Yee Ng | 2025-09-09 |
| 12248021 | Debug trace microsectors | Sean R. Atsatt | 2025-03-11 |
| 12197360 | At-speed burst sampling for user registers | Bee Yee Ng, Gaik Ming Chan | 2025-01-14 |
| 12164462 | Micro-network-on-chip and microsector infrastructure | Ashish Gupta, Chee Hak Teh, Sean R. Atsatt, Scott J. Weber, Parivallal Kannan +2 more | 2024-12-10 |
| 11960734 | Logic fabric based on microsector infrastructure with data register having scan registers | Sean R. Atsatt | 2024-04-16 |
| 11901896 | Soft network-on-chip overlay through a partial reconfiguration region | Scott J. Weber | 2024-02-13 |
| 11789641 | Three dimensional circuit systems and methods having memory hierarchies | Scott J. Weber, Jawad B. Khan, Martin Langhammer, Matthew J. Adiletta, Terence J. Magee +5 more | 2023-10-17 |
| 10340898 | Configurable latch circuit | — | 2019-07-02 |
| 10320386 | Programmable pipeline interface circuit | Brian C. Gaide, Henri Fraisse | 2019-06-11 |
| 10284185 | Selectively providing clock signals using a programmable control circuit | Brian C. Gaide, Chi M. Nguyen, Robert Fu | 2019-05-07 |
| 10230374 | Methods and circuits for preventing hold violations | Benjamin S. Devlin | 2019-03-12 |
| 10069486 | Multimode registers with pulse latches | Benjamin S. Devlin | 2018-09-04 |
| 10049177 | Circuits for and methods of reducing power consumed by routing clock signals in an integrated | Benjamin S. Devlin | 2018-08-14 |
| 9954534 | Methods and circuits for preventing hold time violations | Benjamin S. Devlin, Henri Fraisse | 2018-04-24 |
| 9875330 | Folding duplicate instances of modules in a circuit design | Henri Fraisse, Ashish Sirasao, Alireza S. Kaviani | 2018-01-23 |
| 9842187 | Representation of complex timing characteristics of startpoint-endpoint pairs in a circuit design | Jindrich Zejda, Atul Srinivasan, Walter A. Manaker, Jr., Benjamin S. Devlin, Satish B. Sivaswamy | 2017-12-12 |
| 9836568 | Programmable integrated circuit design flow using timing-driven pipeline analysis | Aaron Ng, Ronald E. Plyler, Sabyasachi Das, Frederic Revenu | 2017-12-05 |
| 9729153 | Multimode multiplexer-based circuit | Benjamin S. Devlin | 2017-08-08 |
| 9577615 | Circuits for and methods of reducing duty-cycle distortion in an integrated circuit implementing dual-edge clocking | Benjamin S. Devlin | 2017-02-21 |
| 9537491 | Leaf-level generation of phase-shifted clocks using programmable clock delays | Benjamin S. Devlin | 2017-01-03 |
| 9531351 | Configurable latch circuit | Benjamin S. Devlin | 2016-12-27 |
| 9372953 | Increasing operating frequency of circuit designs using dynamically modified timing constraints | Shant Chandrakar | 2016-06-21 |
| 9118310 | Programmable delay circuit block | Benjamin S. Devlin | 2015-08-25 |
| 8988125 | Circuits for and methods of routing signals in an integrated circuit | Manu Jose | 2015-03-24 |