Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Methods and circuits for preventing hold time violations

Methods and circuits for preventing hold time violations

US Patent 9954534 · Granted Apr 24, 2018

Estimated economic value: $30,610,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Systems and methods for configurable interface circuits2025
Circuits and methods for configurable scan chains2025
Debug trace microsectors2025
At-speed burst sampling for user registers2025
Micro-network-on-chip and microsector infrastructure2024
Random reads using multi-port memory and on-chip memory blocks2024
Logic fabric based on microsector infrastructure with data register having scan 2024
Soft network-on-chip overlay through a partial reconfiguration region2024
Three dimensional circuit systems and methods having memory hierarchies2023
Random reads using multi-port memory and on-chip memory blocks2023
Routing in a compilation flow for a heterogeneous multi-core architecture2021
Resolving timing violations in multi-die circuit designs2020