Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12412109 | Machine learning deployment platform | Varun Sharma | 2025-09-09 |
| 12248786 | Instruction set architecture for data processing array control | Xiao Teng, Tejus Siddagangaiah, Bryan Lozano, Ehsan Ghasemi, Rajeev Patwari +5 more | 2025-03-11 |
| 12079158 | Reconfigurable neural engine with extensible instruction set architecture | Sanket Pandit, Jorn Tuyls, Xiao Teng, Rajeev Patwari, Ehsan Ghasemi +1 more | 2024-09-03 |
| 11694066 | Machine learning runtime library for neural network acceleration | Jindrich Zejda, Elliott Delaye, Xiao Teng, Sonal Santan, Soren T. Soe +3 more | 2023-07-04 |
| 11620490 | Multi-layer neural network processing by a neural network accelerator using host communicated merged weights and a package of per-layer instructions | Elliott Delaye, Ehsan Ghasemi, Xiao Teng, Jindrich Zejda, Yongjun Wu +2 more | 2023-04-04 |
| 11568218 | Neural network processing system having host controlled kernel acclerators | Jindrich Zejda, Elliott Delaye, Xiao Teng, Ashish Sirasao | 2023-01-31 |
| 11429848 | Host-directed multi-layer neural network processing via per-layer work requests | Elliott Delaye, Jindrich Zejda, Ashish Sirasao | 2022-08-30 |
| 11386644 | Image preprocessing for generalized image processing | Elliott Delaye, Ashish Sirasao, Yongjun Wu, Jindrich Zejda | 2022-07-12 |
| 11222256 | Neural network processing system having multiple processors and a neural network accelerator | Xiao Teng, Ashish Sirasao, Elliott Delaye | 2022-01-11 |
| 11204747 | Re-targetable interface for data exchange between heterogeneous systems and accelerator abstraction into software instructions | Jindrich Zejda, Elliott Delaye, Yongjun Wu, Ashish Sirasao, Khang K. Dao +1 more | 2021-12-21 |
| 11036827 | Software-defined buffer/transposer for general matrix multiplication in a programmable IC | Jindrich Zejda, Elliott Delaye, Yongjun Wu, Ashish Sirasao, Khang K. Dao | 2021-06-15 |
| 10984500 | Inline image preprocessing for convolution operations using a matrix multiplier on an integrated circuit | Ashish Sirasao, Elliott Delaye, Ehsan Ghasemi | 2021-04-20 |
| 10943039 | Software-driven design optimization for fixed-point multiply-accumulate circuitry | Ashish Sirasao, Elliott Delaye, Sean Settle, Zhao Ma, Ehsan Ghasemi +2 more | 2021-03-09 |
| 10936311 | Sparse matrix processing circuitry | Ling Liu, Yifei Zhou, Xiao Teng, Ashish Sirasao, Chuanhua Song | 2021-03-02 |
| 10678509 | Software-driven design optimization for mapping between floating-point and fixed-point multiply accumulators | Sean Settle, Elliott Delaye, Ehsan Ghasemi, Ashish Sirasao, Xiao Teng +1 more | 2020-06-09 |
| 10515135 | Data format suitable for fast massively parallel general matrix multiplication in a programmable IC | Jindrich Zejda, Elliott Delaye, Ashish Sirasao, Yongjun Wu | 2019-12-24 |
| 10460416 | Inline image preprocessing for convolution operations using a matrix multiplier on an integrated circuit | Ashish Sirasao, Elliott Delaye, Ehsan Ghasemi | 2019-10-29 |
| 10366201 | Timing closure of circuit designs for integrated circuits | Sridhar Krishnamurthy, Grigor S. Gasparyan | 2019-07-30 |
| 10354733 | Software-defined memory bandwidth reduction by hierarchical stream buffering for general matrix multiplication in a programmable IC | Jindrich Zejda, Elliott Delaye, Ashish Sirasao, Yongjun Wu | 2019-07-16 |
| 10192016 | Neural network based physical synthesis for circuit designs | Sabyasachi Das, Prabal Basu | 2019-01-29 |
| 9965581 | Fanout optimization to facilitate timing improvement in circuit designs | Sabyasachi Das, Ruibing Lu, Niyati Shah, Zhiyong Wang | 2018-05-08 |
| 9836568 | Programmable integrated circuit design flow using timing-driven pipeline analysis | Ilya K. Ganusov, Ronald E. Plyler, Sabyasachi Das, Frederic Revenu | 2017-12-05 |
| 9646126 | Post-routing structural netlist optimization for circuit designs | Ruibing Lu, Zhiyong Wang, Sabyasachi Das | 2017-05-09 |
| 7840919 | Resource mapping of functional areas on an integrated circuit | Qiang Wang, Rajat Aggarwal | 2010-11-23 |