Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Ruibing Lu — 11 Patents

AMD: 10 patents #1,269 of 9,280Top 15%
Santa Clara, CA: #1,605 of 9,301 inventorsTop 20%
California: #56,011 of 386,348 inventorsTop 15%
Overall (All Time): #435,149 of 4,157,543Top 15%
11 Patents All Time
Ruibing Lu has been granted 11 US patents while listed as an inventor at AMD. The first was granted in 2015 and the most recent in December 2025. Ruibing Lu ranks #435,149 of 4,157,543 US inventors in our database (top 10.5%). Patent records list Ruibing Lu in Santa Clara, CA, US.

Issued Patents All Time

Showing 1–11 of 11 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12500080 Systems and methods for depositing low-K dielectric films Shruba Gangopadhyay, Bhaskar Jyoti Bhuyan, Michael Haverty, Bo Xie, Li-Qun Xia +5 more 2025-12-16
10839125 Post-placement and post-routing physical synthesis for multi-die integrated circuits Sreesan Venkatakrishnan, Sabyasachi Das 2020-11-17 $30,681,000
10699053 Timing optimization of memory blocks in a programmable IC Zhiyong Wang, Lin CHAI, Sabyasachi Das 2020-06-30 $33,305,000
10565334 Targeted delay optimization through programmable clock delays Sabyasachi Das 2020-02-18 $44,383,000
9965581 Fanout optimization to facilitate timing improvement in circuit designs Sabyasachi Das, Aaron Ng, Niyati Shah, Zhiyong Wang 2018-05-08 $22,720,000
9767247 Look-up table restructuring for timing closure in circuit designs Sabyasachi Das 2017-09-19 $82,042,000
9646126 Post-routing structural netlist optimization for circuit designs Zhiyong Wang, Aaron Ng, Sabyasachi Das 2017-05-09 $34,444,000
9613173 Interactive multi-step physical synthesis Rajat Aggarwal, Zhiyong Wang, Sabyasachi Das 2017-04-04 $28,466,000
9483597 Opportunistic candidate path selection during physical optimization of a circuit design for an IC Sabyasachi Das, Zhiyong Wang 2016-11-01 $14,332,000
9235660 Selective addition of clock buffers to a circuit design Sabyasachi Das, Zhiyong Wang 2016-01-12 $4,795,000
8984462 Physical optimization for timing closure for an integrated circuit Sabyasachi Das, Zhiyong Wang, Aman Gayasen 2015-03-17 $11,132,000