Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10839125 | Post-placement and post-routing physical synthesis for multi-die integrated circuits | Sreesan Venkatakrishnan, Sabyasachi Das | 2020-11-17 |
| 10699053 | Timing optimization of memory blocks in a programmable IC | Zhiyong Wang, Lin CHAI, Sabyasachi Das | 2020-06-30 |
| 10565334 | Targeted delay optimization through programmable clock delays | Sabyasachi Das | 2020-02-18 |
| 9965581 | Fanout optimization to facilitate timing improvement in circuit designs | Sabyasachi Das, Aaron Ng, Niyati Shah, Zhiyong Wang | 2018-05-08 |
| 9767247 | Look-up table restructuring for timing closure in circuit designs | Sabyasachi Das | 2017-09-19 |
| 9646126 | Post-routing structural netlist optimization for circuit designs | Zhiyong Wang, Aaron Ng, Sabyasachi Das | 2017-05-09 |
| 9613173 | Interactive multi-step physical synthesis | Rajat Aggarwal, Zhiyong Wang, Sabyasachi Das | 2017-04-04 |
| 9483597 | Opportunistic candidate path selection during physical optimization of a circuit design for an IC | Sabyasachi Das, Zhiyong Wang | 2016-11-01 |
| 9235660 | Selective addition of clock buffers to a circuit design | Sabyasachi Das, Zhiyong Wang | 2016-01-12 |
| 8984462 | Physical optimization for timing closure for an integrated circuit | Sabyasachi Das, Zhiyong Wang, Aman Gayasen | 2015-03-17 |