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Instruction set architecture for data processing array control |
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Scalable acceleration of reentrant compute operations |
Rajeev Patwari, Jorn Tuyls, Elliott Delaye, Ephrem C. Wu |
2024-11-19 |
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Reconfigurable neural engine with extensible instruction set architecture |
Sanket Pandit, Jorn Tuyls, Rajeev Patwari, Ehsan Ghasemi, Elliott Delaye +1 more |
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Machine learning runtime library for neural network acceleration |
Aaron Ng, Jindrich Zejda, Elliott Delaye, Sonal Santan, Soren T. Soe +3 more |
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Multi-layer neural network processing by a neural network accelerator using host communicated merged weights and a package of per-layer instructions |
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Neural network processing system having host controlled kernel acclerators |
Aaron Ng, Jindrich Zejda, Elliott Delaye, Ashish Sirasao |
2023-01-31 |
| 11222256 |
Neural network processing system having multiple processors and a neural network accelerator |
Aaron Ng, Ashish Sirasao, Elliott Delaye |
2022-01-11 |
| 10943039 |
Software-driven design optimization for fixed-point multiply-accumulate circuitry |
Ashish Sirasao, Elliott Delaye, Sean Settle, Zhao Ma, Ehsan Ghasemi +2 more |
2021-03-09 |
| 10936311 |
Sparse matrix processing circuitry |
Ling Liu, Yifei Zhou, Ashish Sirasao, Chuanhua Song, Aaron Ng |
2021-03-02 |
| 10678509 |
Software-driven design optimization for mapping between floating-point and fixed-point multiply accumulators |
Sean Settle, Elliott Delaye, Aaron Ng, Ehsan Ghasemi, Ashish Sirasao +1 more |
2020-06-09 |