Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10162916 | Timing verification in a programmable circuit design using variation factors | Usha Narasimha, Nagaraj Savithri | 2018-12-25 |
| 9864830 | Method and apparatus for placement and routing of circuit designs | Pradip K. Jha, Steven Banks, Nicholas A. Mezei | 2018-01-09 |
| 9842187 | Representation of complex timing characteristics of startpoint-endpoint pairs in a circuit design | Jindrich Zejda, Ilya K. Ganusov, Walter A. Manaker, Jr., Benjamin S. Devlin, Satish B. Sivaswamy | 2017-12-12 |
| 9405871 | Determination of path delays in circuit designs | Nagaraj Savithri, Vinod Kumar Nakkala, Sudip K. Nag | 2016-08-02 |
| 7092838 | Method and apparatus for the analysis and optimization of variability in nanometer technologies | Prasanna Venkat Srinivas, Shankar Krishnamoorthy | 2006-08-15 |