Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10289784 | Determination of clock path delays and implementation of a circuit design | Chiao Kai Hwang, Zicheng Gary Ling | 2019-05-14 |
| 10162916 | Timing verification in a programmable circuit design using variation factors | Usha Narasimha, Atul Srinivasan | 2018-12-25 |
| 9915696 | Area-efficient performance monitors for adaptive voltage scaling | Fu-Hing Ho | 2018-03-13 |
| 9885750 | Speed model tuning for programmable integrated circuits with consideration of device yield, simulated frequency of operation, and speed of device components | — | 2018-02-06 |
| 9639640 | Generation of delay values for a simulation model of circuit elements in a clock network | Robert M. Ondris, Chiao Kai Hwang | 2017-05-02 |
| 9501604 | Testing critical paths of a circuit design | Geetesh MORE, Srinivasan Dasasathyan | 2016-11-22 |
| 9405871 | Determination of path delays in circuit designs | Vinod Kumar Nakkala, Atul Srinivasan, Sudip K. Nag | 2016-08-02 |
| 9372948 | Interconnect speed model characterization in programmable integrated circuits | — | 2016-06-21 |
| 9065446 | Generating delay values for different contexts of a circuit | Amit Gupta, Fu-Hing Ho | 2015-06-23 |
| 8112737 | Contact resistance and capacitance for semiconductor devices | Dharin N. Shah, Girishankar Gurumurthy | 2012-02-07 |
| 8013635 | Multi-mode circuit and a method for preventing degradation in the multi-mode circuit | Palkesh Jain, Usha Narasimha | 2011-09-06 |
| 7694269 | Method for positioning sub-resolution assist features | Mark E. Mason, William R. McKee | 2010-04-06 |
| 7441218 | Contact resistance and capacitance for semiconductor devices | Dharin N. Shah, Girishankar Gurumurthy | 2008-10-21 |
| 7318208 | Method for circuit sensitivity driven parasitic extraction | Usha Narasimha, Anthony M. Hill | 2008-01-08 |
| 7129696 | Method for capacitance measurement in silicon | — | 2006-10-31 |
| 7109738 | Method for modeling inductive effects on circuit performance | — | 2006-09-19 |
| 6732339 | Cell-based noise characterization and evaluation | John Apostol, Anthony M.-Hill | 2004-05-04 |
| 6700399 | High density parasitic measurement structure | — | 2004-03-02 |
| 6499131 | Method for verification of crosstalk noise in a CMOS design | Franciso A. Cano | 2002-12-24 |
| 6493853 | Cell-based noise characterization and evaluation | John Apostol, Anthony M. Hill | 2002-12-10 |
| 6378109 | Method of simulation for gate oxide integrity check on an entire IC | Duane J. Young, Franciso A. Cano | 2002-04-23 |
| 6363516 | Method for hierarchical parasitic extraction of a CMOS design | Francisco A. Cano, Vijaya Gunturi | 2002-03-26 |
| 6253359 | Method for analyzing circuit delays caused by capacitive coupling in digital circuits | Francisco A. Cano, Deepak Kapoor | 2001-06-26 |
| 6038383 | Method and apparatus for determining signal line interconnect widths to ensure electromigration reliability | Duane J. Young, Francisco A. Cano, Haldun Haznedar | 2000-03-14 |