Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10203718 | Generating delays of exit points for a clock circuit | — | 2019-02-12 |
| 10162916 | Timing verification in a programmable circuit design using variation factors | Atul Srinivasan, Nagaraj Savithri | 2018-12-25 |
| 8013635 | Multi-mode circuit and a method for preventing degradation in the multi-mode circuit | Palkesh Jain, Nagaraj Savithri | 2011-09-06 |
| 7363604 | Accurate noise modeling in digital designs | Anthony M. Hill, John Apostol | 2008-04-22 |
| 7318208 | Method for circuit sensitivity driven parasitic extraction | Anthony M. Hill, Nagaraj Savithri | 2008-01-08 |