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Self-time scheme for optimizing performance and power in dual rail power supplies memories |
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Circuits for pulse-width control in memory devices and related methods |
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2019-06-11 |
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Read-current and word line delay path tracking for sense amplifier enable timing |
Anand Seshadri, Parvinder Kumar Rana, Wah Kit Loh |
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Error prediction in logic and memory devices |
Sharad Gupta, Vinod Menezes, Vish Visvanathan |
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Error prediction in logic and memory devices |
Sharad Gupta, Vinod Menezes, Vish Visvanathan |
2014-06-24 |
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Digital storage element architecture comprising integrated 2-to-1 multiplexer functionality |
Charles M. Branch, Steven Craig Bartling |
2014-04-08 |
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Improving routability of integrated circuit design without impacting the design area |
Pavan Vithal Torvi, Girishankar Gurumurthy, Ajith Harihara Subramonia |
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Contact resistance and capacitance for semiconductor devices |
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2012-02-07 |
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Generation of standard cell library components with increased signal routing resources |
Clive Bittlestone, Graham McLeod Barr, Girishankar Gurumurthy, Pavan Vithal Torvi |
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Cell supporting scan-based tests and with reduced time delay in functional mode |
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2010-09-07 |
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Slave latch controlled retention flop with lower leakage and higher performance |
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2009-09-29 |
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2009-02-03 |
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Contact resistance and capacitance for semiconductor devices |
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2008-10-21 |
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Digital storage element with dual behavior |
Charles M. Branch, Steven Craig Bartling, James R. Hochschild |
2008-03-18 |
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Digital storage element architecture comprising integrated 4-to-1 multiplexer functionality |
Charles M. Branch, Steven Craig Bartling |
2007-09-25 |
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Digital storage element architecture comprising integrated multiplexer and reset functionality |
Charles M. Branch, Steven Craig Bartling |
2007-09-25 |