Issued Patents All Time
Showing 25 most recent of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12327599 | Memory with scan chain testing of column redundancy logic and multiplexing | Rahul Sahu, Jung Pill Kim, Chulmin Jung, Jais Abraham | 2025-06-10 |
| 12210373 | Low overhead mesochronous digital interface | Ankur Bal, Anupam Jain | 2025-01-28 |
| 12183393 | High-speed multi-port memory supporting collision | Pradeep Raj, Rahul Sahu | 2024-12-31 |
| 12047073 | Power supply circuit with reduced leakage current | Pradeep Raj, Rahul Sahu, Chulmin Jung | 2024-07-23 |
| 12020766 | Memory circuit architecture with multiplexing between memory banks | Pradeep Raj, Rahul Sahu, Hemant Patel, Diwakar SINGH | 2024-06-25 |
| 11979167 | Low power and high speed data weighted averaging (DWA) to binary converter circuit | Ankur Bal | 2024-05-07 |
| 11972834 | Low power and robust level-shifting pulse latch for dual-power memories | Adithya Bhaskaran, Rahul Sahu | 2024-04-30 |
| 11955169 | High-speed multi-port memory supporting collision | Pradeep Raj, Rahul Sahu | 2024-04-09 |
| 11935606 | Memory with scan chain testing of column redundancy logic and multiplexing | Rahul Sahu, Jung Pill Kim, Chulmin Jung, Jais Abraham | 2024-03-19 |
| 11933861 | Phase-independent testing of a converter | Ankur Bal | 2024-03-19 |
| 11909410 | Sigma-delta analog-to-digital converter circuit with real time correction for digital-to-analog converter mismatch error | Ankur Bal | 2024-02-20 |
| 11901919 | On chip test architecture for continuous time delta sigma analog-to-digital converter | Ankur Bal, Abhishek Jain | 2024-02-13 |
| 11837313 | Memory with efficient DVS controlled by asynchronous inputs | Pradeep Raj, Rahul Sahu, Chulmin Jung | 2023-12-05 |
| 11522553 | Sigma-delta analog-to-digital converter circuit with real time correction for digital-to-analog converter mismatch error | Ankur Bal | 2022-12-06 |
| 11228312 | Wide voltage range level shifter with reduced duty cycle distortion across operating conditions | Narender Ponna, Akhtar ALAM | 2022-01-18 |
| 11152921 | Systems and methods for control signal latching in memories | Veerabhadra Rao Boda, Rahul Sahu | 2021-10-19 |
| 11049552 | Write assist circuitry for memory | Pradeep Raj, Rahul Sahu, Chulmin Jung | 2021-06-29 |
| 11043271 | Reusing a cell block for hybrid dual write | Arun Kumar Shukla, Silky Mohanty, Athira Kanchiyil, Arunkumar Mani, Noor Mohamed | 2021-06-22 |
| 11037627 | Cell block allocation for hybrid dual write | Arun Kumar Shukla, Silky Mohanty, Athira Kanchiyil, Arunkumar Mani, Noor Mohamed | 2021-06-15 |
| 10867668 | Area efficient write data path circuit for SRAM yield enhancement | Pradeep Raj, Rahul Sahu, Mukund Narasimhan | 2020-12-15 |
| 10811086 | SRAM write yield enhancement with pull-up strength modulation | Shiba Mohanty, Rahul Sahu, Pradeep Raj, Veerabhadra Rao Boda, Adithya Bhaskaran +1 more | 2020-10-20 |
| 10811088 | Access assist with wordline adjustment with tracking cell | Pradeep Raj, Rahul Sahu | 2020-10-20 |
| 10732838 | Logical grouping for hybrid dual write | Noor Mohamed, Athira Kanchiyil, Arunkumar Mani, Silky Mohanty, Arun Kumar Shukla | 2020-08-04 |
| 10560698 | Graphics server and method for streaming rendered content via a remote graphics processing service | Thomas Meier, Chong Zhang, Bhanu Prashanthi Murthy, Karthik Vijayan | 2020-02-11 |
| 10446196 | Flexible power sequencing for dual-power memory | Mukund Narasimhan, Adithya Bhaskaran, Sei Seung Yoon | 2019-10-15 |