Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12327599 | Memory with scan chain testing of column redundancy logic and multiplexing | Rahul Sahu, Sharad Gupta, Jung Pill Kim, Chulmin Jung | 2025-06-10 |
| 11935606 | Memory with scan chain testing of column redundancy logic and multiplexing | Rahul Sahu, Sharad Gupta, Jung Pill Kim, Chulmin Jung | 2024-03-19 |
| 10996267 | Time interleaved scan system | Punit Kishore | 2021-05-04 |
| 10656203 | Low pin count test controller | Punit Kishore, Pawan Chhabra | 2020-05-19 |
| 7421634 | Sequential scan based techniques to test interface between modules designed to operate at different frequencies | Naga Satya Srikanth Puvvada, Nikila Krishnamoorthy, Sandeep Jain | 2008-09-02 |
| 7404126 | Scan tests tolerant to indeterminate states when employing signature analysis to analyze test outputs | Sandeep Jain | 2008-07-22 |
| 7352169 | Testing components of I/O paths of an integrated circuit | Rohit Goel | 2008-04-01 |
| 7082558 | Increasing possible test patterns which can be used with sequential scanning techniques to perform speed analysis | Ajit Deepak Gupte, Shankaranarayana Karantha Deshamangala, Amit Brahme | 2006-07-25 |
| 6981190 | Controlling the content of specific desired memory elements when testing integrated circuits using sequential scanning techniques | Ajit Deepak Gupte | 2005-12-27 |
| 6853212 | Gated scan output flip-flop | G. Subash Chandar | 2005-02-08 |