Issued Patents All Time
Showing 25 most recent of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12327599 | Memory with scan chain testing of column redundancy logic and multiplexing | Sharad Gupta, Jung Pill Kim, Chulmin Jung, Jais Abraham | 2025-06-10 |
| 12183393 | High-speed multi-port memory supporting collision | Pradeep Raj, Sharad Gupta | 2024-12-31 |
| 12047073 | Power supply circuit with reduced leakage current | Pradeep Raj, Sharad Gupta, Chulmin Jung | 2024-07-23 |
| 12020746 | Memory write assist with reduced switching power | Rejeesh Ammanath Vijayan, Pradeep Raj | 2024-06-25 |
| 12020766 | Memory circuit architecture with multiplexing between memory banks | Pradeep Raj, Sharad Gupta, Hemant Patel, Diwakar SINGH | 2024-06-25 |
| 11972834 | Low power and robust level-shifting pulse latch for dual-power memories | Adithya Bhaskaran, Sharad Gupta | 2024-04-30 |
| 11955169 | High-speed multi-port memory supporting collision | Pradeep Raj, Sharad Gupta | 2024-04-09 |
| 11935606 | Memory with scan chain testing of column redundancy logic and multiplexing | Sharad Gupta, Jung Pill Kim, Chulmin Jung, Jais Abraham | 2024-03-19 |
| 11837313 | Memory with efficient DVS controlled by asynchronous inputs | Pradeep Raj, Sharad Gupta, Chulmin Jung | 2023-12-05 |
| 11152921 | Systems and methods for control signal latching in memories | Veerabhadra Rao Boda, Sharad Gupta | 2021-10-19 |
| 11049552 | Write assist circuitry for memory | Pradeep Raj, Sharad Gupta, Chulmin Jung | 2021-06-29 |
| 10867668 | Area efficient write data path circuit for SRAM yield enhancement | Sharad Gupta, Pradeep Raj, Mukund Narasimhan | 2020-12-15 |
| 10839866 | Memory core power-up with reduced peak current | Shiba Mohanty, Channappa Desai | 2020-11-17 |
| 10811086 | SRAM write yield enhancement with pull-up strength modulation | Shiba Mohanty, Sharad Gupta, Pradeep Raj, Veerabhadra Rao Boda, Adithya Bhaskaran +1 more | 2020-10-20 |
| 10811088 | Access assist with wordline adjustment with tracking cell | Pradeep Raj, Sharad Gupta | 2020-10-20 |
| 10614865 | Boost generation circuitry for memory | Shiba Mohanty, Rakesh Sinha | 2020-04-07 |
| 9928898 | Wordline adjustment scheme | Sharad Gupta | 2018-03-27 |
| 9916892 | Write driver circuitry to reduce leakage of negative boost charge | Pradeep Raj, Mukund Narasimhan, Fahad Ahmed, Chulmin Jung | 2018-03-13 |
| 9865337 | Write data path to reduce charge leakage of negative boost | Fahad Ahmed, Mukund Narasimhan, Raghav Gupta, Pradeep Raj, Po-Hung Chen +1 more | 2018-01-09 |
| 9721650 | Architecture to improve write-ability in SRAM | Pradeep Raj, Sharad Gupta, Lakshmikantha Holla Vakwadi | 2017-08-01 |
| 9455028 | Adaptive negative bit line write assist | — | 2016-09-27 |
| 9281055 | Memory sense amplifier and column pre-charger | Dharmendra Kumar Rai | 2016-03-08 |
| 9177635 | Dual rail single-ended read data paths for static random access memories | Donald Albert Evans, Rasoju Veerabadra Chary, Rajiv Roy | 2015-11-03 |
| 9177633 | Bit line write assist for static random access memory architectures | Rajiv Roy, Rasoju Veerabadra Chary | 2015-11-03 |
| 9111637 | Differential latch word line assist for SRAM | Rajiv Roy, Rasoju Veerabadra Chary, Dharmendra Kumar Rai | 2015-08-18 |