| 12183393 |
High-speed multi-port memory supporting collision |
Rahul Sahu, Sharad Gupta |
2024-12-31 |
| 12047073 |
Power supply circuit with reduced leakage current |
Rahul Sahu, Sharad Gupta, Chulmin Jung |
2024-07-23 |
| 12020746 |
Memory write assist with reduced switching power |
Rejeesh Ammanath Vijayan, Rahul Sahu |
2024-06-25 |
| 12020766 |
Memory circuit architecture with multiplexing between memory banks |
Rahul Sahu, Sharad Gupta, Hemant Patel, Diwakar SINGH |
2024-06-25 |
| 11955169 |
High-speed multi-port memory supporting collision |
Rahul Sahu, Sharad Gupta |
2024-04-09 |
| 11837313 |
Memory with efficient DVS controlled by asynchronous inputs |
Rahul Sahu, Sharad Gupta, Chulmin Jung |
2023-12-05 |
| 11049552 |
Write assist circuitry for memory |
Rahul Sahu, Sharad Gupta, Chulmin Jung |
2021-06-29 |
| 10867668 |
Area efficient write data path circuit for SRAM yield enhancement |
Sharad Gupta, Rahul Sahu, Mukund Narasimhan |
2020-12-15 |
| 10811086 |
SRAM write yield enhancement with pull-up strength modulation |
Shiba Mohanty, Sharad Gupta, Rahul Sahu, Veerabhadra Rao Boda, Adithya Bhaskaran +1 more |
2020-10-20 |
| 10811088 |
Access assist with wordline adjustment with tracking cell |
Rahul Sahu, Sharad Gupta |
2020-10-20 |
| 9916892 |
Write driver circuitry to reduce leakage of negative boost charge |
Rahul Sahu, Mukund Narasimhan, Fahad Ahmed, Chulmin Jung |
2018-03-13 |
| 9865337 |
Write data path to reduce charge leakage of negative boost |
Fahad Ahmed, Mukund Narasimhan, Raghav Gupta, Rahul Sahu, Po-Hung Chen +1 more |
2018-01-09 |
| 9721650 |
Architecture to improve write-ability in SRAM |
Sharad Gupta, Rahul Sahu, Lakshmikantha Holla Vakwadi |
2017-08-01 |
| 9478278 |
Read-write contention circuitry |
Rejeesh Ammanath Vijayan, Vikash, Neelima Gudipati, Manish Trivedi, Sujit Kumar Rout |
2016-10-25 |