Issued Patents All Time
Showing 25 most recent of 95 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12367927 | Pseudo-differential de-glitch sense amplifier | David Li, Po-Hung Chen, Ayan Paul, Derek Yang, Chun-Yen Lin | 2025-07-22 |
| 12341497 | Power multiplexer | Harshat Pant, Hanil Lee, Shih-Hsin Jason Hu, Xiao Chen, Christol Barnes | 2025-06-24 |
| 12334143 | Power level comparator with switching input | Seohee KIM, Xiao Chen, Hanil Lee, Venugopal Boynapalli, Jung Pill Kim | 2025-06-17 |
| 12327599 | Memory with scan chain testing of column redundancy logic and multiplexing | Rahul Sahu, Sharad Gupta, Jung Pill Kim, Jais Abraham | 2025-06-10 |
| 12125526 | Memory with bitcell power boosting | Xiao Chen, Chi-Jui Chen, Anil Chowdary Kota, Dhvani Sheth | 2024-10-22 |
| 12094528 | Memory with double redundancy | Dhvani Sheth, Hochul Lee, Anil Chowdary Kota | 2024-09-17 |
| 12047073 | Power supply circuit with reduced leakage current | Pradeep Raj, Rahul Sahu, Sharad Gupta | 2024-07-23 |
| 12014771 | Method of pseudo-triple-port SRAM datapaths | Changho Jung, Arun Babu Pallerla | 2024-06-18 |
| 11935606 | Memory with scan chain testing of column redundancy logic and multiplexing | Rahul Sahu, Sharad Gupta, Jung Pill Kim, Jais Abraham | 2024-03-19 |
| 11894050 | Memory with a sense amplifier isolation scheme for enhancing memory read bandwidth | Hochul Lee, Anil Chowdary Kota, Dhvani Sheth | 2024-02-06 |
| 11837313 | Memory with efficient DVS controlled by asynchronous inputs | Pradeep Raj, Rahul Sahu, Sharad Gupta | 2023-12-05 |
| 11670351 | Memory with single-ended sensing using reset-set latch | Arun Babu Pallerla, Anil Chowdary Kota, Changho Jung | 2023-06-06 |
| 11640838 | Pseudo-dual-port SRAM with burst-mode address comparator | Arun Babu Pallerla, Changho Jung | 2023-05-02 |
| 11615837 | Pseudo-triple-port SRAM datapaths | Changho Jung, Arun Babu Pallerla | 2023-03-28 |
| 11610633 | Low-leakage drain-programmed ROM | Xiao Chen, Chen-ju Hsieh, Sung Son | 2023-03-21 |
| 11527282 | SRAM with burst mode operation | Changho Jung, Keejong Kim, Ritu Chaba | 2022-12-13 |
| 11488658 | Write assist scheme with bitline | Bin Liang, Chi-Jui Chen | 2022-11-01 |
| 11462263 | Burst-mode memory with column multiplexer | Changho Jung, Arun Babu Pallerla | 2022-10-04 |
| 11450359 | Memory write methods and circuits | Xiao Chen, Po-Hung Chen, Chen-ju Hsieh, David Li, Ayan Paul | 2022-09-20 |
| 11361817 | Pseudo-triple-port SRAM bitcell architecture | Arun Babu Pallerla, Changho Jung, Sung Son, Jason Michael Cheng, Yandong Gao +1 more | 2022-06-14 |
| 11250895 | Systems and methods for driving wordlines using set-reset latches | Dhvani Sheth, Anil Chowdary Kota, Hochul Lee, Bin Liang | 2022-02-15 |
| 11170845 | Techniques for reducing rock bottom leakage in memory | Arun Babu Pallerla, Derek Yang, Changho Jung | 2021-11-09 |
| 11170865 | Area-efficient dynamic memory redundancy scheme with priority decoding | Bin Liang, Chi-Jui Chen | 2021-11-09 |
| 11092646 | Determining a voltage and/or frequency for a performance mode | Sonia Ghosh, Changho Jung | 2021-08-17 |
| 11049552 | Write assist circuitry for memory | Pradeep Raj, Rahul Sahu, Sharad Gupta | 2021-06-29 |