Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12341497 | Power multiplexer | Hanil Lee, Shih-Hsin Jason Hu, Chulmin Jung, Xiao Chen, Christol Barnes | 2025-06-24 |
| 11687106 | Systems and methods for adaptive power multiplexing with a first type of power multiplexer and a second type of power multiplexer | Giby Samson, Keyurkumar Karsanbhai Kansagra, Mohammed Yousuff Shariff, Vinayak Nana MEHETRE | 2023-06-27 |
| 11249530 | Adaptive voltage controller | Dipti Ranjan Pal, Abinash ROY, Shih-Hsin Jason Hu, Keith Alan Bowman | 2022-02-15 |
| 11177805 | Reducing glitch power in digital circuits | Ravindraraj Ramaraju, Luis Filipe Brochado Reis, Tuck Boon Chan, Mayank Sen Sharma | 2021-11-16 |
| 11157066 | Floorplan independent and cross-current-free distributed power switch | Byron Murphy, Rajeev Jain, Lipeng Cao | 2021-10-26 |
| 10712807 | Methods and apparatus for saving always on (AON) routing of signals across chips | Rajeev Jain, Byron Murphy, Lipeng Cao | 2020-07-14 |
| 10401941 | Clock glitch prevention for retention operational mode | Ramprasath Vilangudipitchai, Srijith Nair, Mohammad Tamjidi | 2019-09-03 |
| 10317968 | Power multiplexing with an active load | Rajeev Jain, Sassan Shahrokhinia, Lam Ho | 2019-06-11 |
| 10109619 | Methods and apparatus for using split N-well cells in a merged N-well block | Mohammed Yousuff Shariff, Parissa Najdesamii, Ramaprasath Vilangudipitchai, Divjyot Bhan | 2018-10-23 |
| 9973187 | Circuits and methods providing power on reset signals | Aditya Vummannagari, Yeshwant Nagaraj Kolla | 2018-05-15 |
| 9665160 | Unified retention flip-flop architecture and control | Lipeng Cao, Divjyot Bhan, Ramaprasath Vilangudipitchai | 2017-05-30 |
| 9473113 | Power management with flip-flops | Ramaprasath Vilangudipitchai, Divjyot Bhan, Lipeng Cao, Sai Pradeep Kochuri, Parissa Najdesamii | 2016-10-18 |