Issued Patents All Time
Showing 25 most recent of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12431877 | Hybrid flop tray including different fin size flip-flops | Ramaprasath Vilangudipitchai, Rui-Hua Chen, Seung H. Kang | 2025-09-30 |
| 12334143 | Power level comparator with switching input | Seohee KIM, Chulmin Jung, Xiao Chen, Hanil Lee, Jung Pill Kim | 2025-06-17 |
| 12323142 | Integrated power management cells for gate all around technologies | Ramaprasath Vilangudipitchai, Venkat Narayanan, Giby Samson | 2025-06-03 |
| 11710733 | Vertical power grid standard cell architecture | Hyeokjin Lim, Bharani Chava, Foua Vang, Seung H. Kang | 2023-07-25 |
| 11437379 | Field-effect transistors (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals, and related complementary metal oxide semiconductor (CMOS) circuits | Stanley Seungchul Song, Deepak Sharma, Bharani Chava, Hyeokjin Lim, Peijie Feng +6 more | 2022-09-06 |
| 11361817 | Pseudo-triple-port SRAM bitcell architecture | Arun Babu Pallerla, Changho Jung, Sung Son, Jason Michael Cheng, Yandong Gao +1 more | 2022-06-14 |
| 11290109 | Multibit multi-height cell to improve pin accessibility | Foua Vang, Hyeokjin Lim, Seung H. Kang, Shitiz Arora | 2022-03-29 |
| 11237580 | Systems and methods providing leakage reduction for power gated domains | Giby Samson, Foua Vang, Ramaprasath Vilangudipitchai, Seung H. Kang | 2022-02-01 |
| 11133803 | Multiple via structure for high performance standard cells | Satyanarayana Sahu, Xiangdong Chen, Hyeokjin Lim, Mickael Malabry, Mukul Gupta | 2021-09-28 |
| 10965289 | Metal oxide semiconductor device of an integrated circuit | Satyanarayana Sahu, Xiangdong Chen, Hyeokjin Lim, Mickael Malabry, Mukul Gupta | 2021-03-30 |
| 10784345 | Standard cell architecture for gate tie-off | Xiangdong Chen, Hyeokjin Lim | 2020-09-22 |
| 10777640 | Standard cell architecture for gate tie-off | Xiangdong Chen, Hyeokjin Lim | 2020-09-15 |
| 10692808 | High performance cell design in a technology with high density metal routing | Renukprasad HIREMATH, Hyeokjin Lim, Foua Vang, Xiangdong Chen | 2020-06-23 |
| 10600866 | Standard cell architecture for gate tie-off | Xiangdong Chen, Hyeokjin Lim | 2020-03-24 |
| 10490543 | Placement methodology to remove filler | Xiangdong Chen, Sorin Adrian Dobre, Hyeokjin Lim | 2019-11-26 |
| 10236886 | Multiple via structure for high performance standard cells | Satyanarayana Sahu, Xiangdong Chen, Hyeokjin Lim, Mickael Malabry, Mukul Gupta | 2019-03-19 |
| 10103626 | Digital power multiplexor | Venkatasubramanian Narayanan, Dorav Kumar, Ramaprasath Vilangudipitchai | 2018-10-16 |
| 10038429 | High-speed soft-edge sense-amplifier-based flip-flop | Venkat Narayanan, Qi Ye, Manish Srivastava | 2018-07-31 |
| 9990984 | Pulse-stretcher clock generator circuit for high speed memory subsystems | Dorav Kumar, Venkat Narayanan, Bilal Zafar, Seid Hadi Rasouli | 2018-06-05 |
| 9979381 | Semi-data gated flop with low clock power/low internal power with minimal area overhead | Seid Hadi Rasouli, Xiangdong Chen | 2018-05-22 |
| 9979394 | Pulse-generator | Qi Ye, Animesh Datta, Venkatasubramanian Narayanan | 2018-05-22 |
| 9960231 | Standard cell architecture for parasitic resistance reduction | Xiangdong Chen, Hyeokjin Lim, Satyanarayana Sahu | 2018-05-01 |
| 9831272 | Metal oxide semiconductor cell device architecture with mixed diffusion break isolation trenches | Xiangdong Chen, Satyanarayana Sahu, Hyeokjin Lim, Mukul Gupta | 2017-11-28 |
| 9806717 | High-speed level-shifting multiplexer | Kevin Bowles, Jose Gabriel Corona | 2017-10-31 |
| 9755618 | Low-area low clock-power flip-flop | Seid Hadi Rasouli, Xiangdong Chen | 2017-09-05 |