Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12400966 | Package comprising integrated devices and bridge coupling top sides of integrated devices | Abinash ROY, Stanley Seungchul Song, Jonghae Kim | 2025-08-26 |
| 12057436 | Package comprising an integrated device configured for shareable power resource | Abinash ROY | 2024-08-06 |
| 11876085 | Package with a substrate comprising an embedded capacitor with side wall coupling | Abinash ROY, Lohith Kumar Vemula, Jonghae Kim | 2024-01-16 |
| 11830819 | Package comprising integrated devices and bridge coupling top sides of integrated devices | Abinash ROY, Stanley Seungchul Song, Jonghae Kim | 2023-11-28 |
| 11764186 | Package comprising an integrated device configured for shareable power resource | Abinash ROY | 2023-09-19 |
| 11749327 | Memory bit cell circuit including a bit line coupled to a static random-access memory (SRAM) bit cell circuit and a non-volatile memory (NVM) bit cell circuit and a memory bit cell array circuit | Khaja Ahmad Shaik | 2023-09-05 |
| 11710733 | Vertical power grid standard cell architecture | Hyeokjin Lim, Foua Vang, Seung H. Kang, Venugopal Boynapalli | 2023-07-25 |
| 11668735 | Granular sensing on an integrated circuit | Stefano Facchin, Baptiste Grave, David Jonathan Walshe | 2023-06-06 |
| 11645503 | Multibit neural network | Mohit Gupta, Wim Dehaene, Sushil Sakhare | 2023-05-09 |
| 11552055 | Integrated circuit (IC) packages employing front side back-end-of-line (FS-BEOL) to back side back-end-of-line (BS-BEOL) stacking for three-dimensional (3D) die stacking, and related fabrication methods | Stanley Seungchul Song | 2023-01-10 |
| 11515289 | Stacked die integrated with package voltage regulators | Stanley Seungchul Song, Abinash ROY, Jonghae Kim | 2022-11-29 |
| 11449740 | Synapse circuit with memory | Shairfe Muhammad Salahuddin, Hyungrock Oh | 2022-09-20 |
| 11437379 | Field-effect transistors (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals, and related complementary metal oxide semiconductor (CMOS) circuits | Stanley Seungchul Song, Deepak Sharma, Hyeokjin Lim, Peijie Feng, Seung H. Kang +6 more | 2022-09-06 |
| 11430797 | Package embedded programmable resistor for voltage droop mitigation | Abinash ROY | 2022-08-30 |
| 11270991 | Integrated circuits (ICs) employing front side (FS) back end-of-line (BEOL) (FS-BEOL) input/output (I/O) routing and back side (BS) BEOL (BS-BEOL) power routing for current flow organization, and related methods | Stanley Seungchul Song, Mohammed Yousuff Shariff | 2022-03-08 |
| 11195793 | Metal filling in a dielectric layer under metal layer one (M1)and above an active device layer in semiconductor devices | Stanley Seungchul Song | 2021-12-07 |
| 11176991 | Compute-in-memory (CIM) employing low-power CIM circuits employing static random access memory (SRAM) bit cells, particularly for multiply-and-accumluate (MAC) operations | Khaja Ahmad Shaik, Dawuth Shadulkhan Pathan | 2021-11-16 |