Issued Patents All Time
Showing 1–25 of 102 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12400966 | Package comprising integrated devices and bridge coupling top sides of integrated devices | Bharani Chava, Abinash ROY, Jonghae Kim | 2025-08-26 |
| 11973019 | Deep trench capacitors in an inter-layer medium on an interconnect layer of an integrated circuit die and related methods | Jihong Choi, Giridhar Nallapati, Periannan Chidambaram | 2024-04-30 |
| 11830819 | Package comprising integrated devices and bridge coupling top sides of integrated devices | Bharani Chava, Abinash ROY, Jonghae Kim | 2023-11-28 |
| 11626359 | Three-dimensional integrated circuit (3D IC) power distribution network (PDN) capacitor integration | Biancun Xie, Shree Krishna Pandey, Irfan Khan, Miguel MIRANDA CORBALAN | 2023-04-11 |
| 11552055 | Integrated circuit (IC) packages employing front side back-end-of-line (FS-BEOL) to back side back-end-of-line (BS-BEOL) stacking for three-dimensional (3D) die stacking, and related fabrication methods | Bharani Chava | 2023-01-10 |
| 11545555 | Gate-all-around (GAA) transistors with shallow source/drain regions and methods of fabricating the same | Peijie Feng, Kern Rim | 2023-01-03 |
| 11515289 | Stacked die integrated with package voltage regulators | Bharani Chava, Abinash ROY, Jonghae Kim | 2022-11-29 |
| 11502079 | Integrated device comprising a CMOS structure comprising well-less transistors | Hyunwoo Park, Peijie Feng | 2022-11-15 |
| 11444068 | Three-dimensional (3D) integrated circuit device having a backside power delivery network | Jonghae Kim, Periannan Chidambaram, Pratyush Kamal | 2022-09-13 |
| 11437379 | Field-effect transistors (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals, and related complementary metal oxide semiconductor (CMOS) circuits | Deepak Sharma, Bharani Chava, Hyeokjin Lim, Peijie Feng, Seung H. Kang +6 more | 2022-09-06 |
| 11404374 | Circuits employing a back side-front side connection structure for coupling back side routing to front side routing, and related complementary metal oxide semiconductor (CMOS) circuits and methods | Hyeokjin Lim, Foua Vang, Seung H. Kang | 2022-08-02 |
| 11310911 | Three-dimensional (3D) integrated circuit (IC) integration of an embedded chip and a preformed metal routing structure | Jonghae Kim, Periannan Chidambaram | 2022-04-19 |
| 11302638 | Hybrid conductor integration in power rail | John Jianhong Zhu, Kern Rim | 2022-04-12 |
| 11270991 | Integrated circuits (ICs) employing front side (FS) back end-of-line (BEOL) (FS-BEOL) input/output (I/O) routing and back side (BS) BEOL (BS-BEOL) power routing for current flow organization, and related methods | Bharani Chava, Mohammed Yousuff Shariff | 2022-03-08 |
| 11257917 | Gate-all-around (GAA) transistors with additional bottom channel for reduced parasitic capacitance and methods of fabrication | Jun Yuan, Peijie Feng, Kern Rim | 2022-02-22 |
| 11244895 | Intertwined well connection and decoupling capacitor layout structure for integrated circuits | Ramesh MANCHANA, Sudheer Chowdary Gali, Biswa Ranjan PANDA, Dhaval Sejpal | 2022-02-08 |
| 11195793 | Metal filling in a dielectric layer under metal layer one (M1)and above an active device layer in semiconductor devices | Bharani Chava | 2021-12-07 |
| 11152347 | Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connections | Kern Rim, John Jianhong Zhu, Da Yang | 2021-10-19 |
| 11145654 | Field effect transistor (FET) comprising channels with silicon germanium (SiGe) | Kwanyong LIM, Jun Yuan, Kern Rim | 2021-10-12 |
| 10996261 | Sensor for gate leakage detection | Hyunwoo Park, Youn Sung Choi | 2021-05-04 |
| 10847507 | Contact liner to enable different CPP devices | Junjing Bao, Jie Deng, Giridhar Nallapati | 2020-11-24 |
| 10840884 | Bulk acoustic wave (BAW) and passive-on-glass (POG) filter co-integration | Jonghae Kim, Periannan Chidambaram | 2020-11-17 |
| 10763364 | Circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation, and related methods | Kern Rim, Da Yang, Peijie Feng | 2020-09-01 |
| 10700204 | Circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation, and related methods | Kern Rim, Da Yang, Peijie Feng | 2020-06-30 |
| 10593700 | Standard cell architecture with M1 layer unidirectional routing | Mukul Gupta, Xiangdong Chen, Ohsang Kwon, Foua Vang, Kern Rim | 2020-03-17 |