Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12218041 | Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate for interfacing an IC chip(s) to a package substrate, and related methods | Giridhar Nallapati, William Stone, Jianwen Xu, Jonghae Kim, Periannan Chidambaram +1 more | 2025-02-04 |
| 11973019 | Deep trench capacitors in an inter-layer medium on an interconnect layer of an integrated circuit die and related methods | Stanley Seungchul Song, Giridhar Nallapati, Periannan Chidambaram | 2024-04-30 |
| 10833017 | Contact for semiconductor device | Yanxiang Liu, Haining Yang, Youseok Suh, Junjing Bao | 2020-11-10 |
| 9941156 | Systems and methods to reduce parasitic capacitance | Shiqun Gu, Vidhya Ramachandran, Christine Hau-Riege, John Jianhong Zhu, Jeffrey Junhao Xu +2 more | 2018-04-10 |
| 9269492 | Bone frame, low resistance via coupled metal oxide-metal (MOM) orthogonal finger capacitor | John Jianhong Zhu, PR Chidambaram, Lixin Ge, Bin Yang | 2016-02-23 |
| 9252104 | Complementary back end of line (BEOL) capacitor | John Jianhong Zhu, Bin Yang, PR Chidambaram, Lixin Ge | 2016-02-02 |
| 9245971 | Semiconductor device having high mobility channel | Bin Yang, P R Chidambaram, John Jianhong Zhu, Da Yang, Ravi M. Todi +4 more | 2016-01-26 |
| 8980708 | Complementary back end of line (BEOL) capacitor | John Jianhong Zhu, Bin Yang, P R Chidambaram, Lixin Ge | 2015-03-17 |
| 8241927 | Methods relating to capacitive monitoring of layer characteristics during back end-of the-line processing | Yongsik Moon, Roderick A. Augur, Eden Zielinski | 2012-08-14 |
| 8105942 | CMP-first damascene process scheme | Tibor Bolom | 2012-01-31 |