Issued Patents All Time
Showing 25 most recent of 78 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12342595 | Transistor cell with self-aligned gate contact | John Jianhong Zhu, Giridhar Nallapati | 2025-06-24 |
| 12068238 | Back-end-of-line (BEOL) high resistance (Hi-R) conductor layer in a metal oxide metal (MOM) capacitor | John Jianhong Zhu, Haining Yang | 2024-08-20 |
| 12057394 | Three-dimensional (3D) interconnect structures employing via layer conductive structures in via layers and related fabrication methods | Xia Li, Bin Yang | 2024-08-06 |
| 11942414 | Integrated circuits (ICs) employing directly coupled metal lines between vertically-adjacent interconnect layers for reduced coupling resistance, and related methods | John Jianhong Zhu, Giridhar Nallapati | 2024-03-26 |
| 11901427 | Gate contact isolation in a semiconductor | Haining Yang | 2024-02-13 |
| 11901434 | Semiconductor having a source/drain contact with a single inner spacer | Haining Yang, Youseok Suh | 2024-02-13 |
| 11855198 | Multi-gate high electron mobility transistors (HEMTs) employing tuned recess depth gates for improved device linearity | Chenjie TANG, Ye Lu, Peijie Feng | 2023-12-26 |
| 11710789 | Three dimensional (3D) double gate semiconductor | Xia Li, Bin Yang | 2023-07-25 |
| 11411092 | Field effect transistor (FET) comprising inner spacers and voids between channels | Ye Lu, Peijie Feng, Chenjie TANG | 2022-08-09 |
| 11404373 | Hybrid low resistance metal lines | John Jianhong Zhu, Giridhar Nallapati | 2022-08-02 |
| 11387335 | Optimized contact structure | Jun Yuan, Peijie Feng | 2022-07-12 |
| 11380685 | Semiconductor device with superlattice fin | Ye Lu, Chenjie TANG, Peijie Feng | 2022-07-05 |
| 11335683 | Device channel profile structure | Haining Yang, ChihWei Kuo | 2022-05-17 |
| 11302773 | Back-end-of-line integrated metal-insulator-metal capacitor | Ye Lu, Haitao Cheng, Chao Song | 2022-04-12 |
| 11295991 | Complementary cell circuits employing isolation structures for defect reduction and related methods of fabrication | Haining Yang | 2022-04-05 |
| 11289365 | Air gap underneath passive devices | Ye Lu, Haitao Cheng | 2022-03-29 |
| 11239307 | Metal-oxide-metal capacitor from subtractive back-end-of-line scheme | John Jianhong Zhu, Ye Lu | 2022-02-01 |
| 11189617 | Gate-all-around devices with reduced parasitic capacitance | Peijie Feng, Ye Lu, Chenjie TANG | 2021-11-30 |
| 11164952 | Transistor with insulator | Ye Lu, Haining Yang | 2021-11-02 |
| 11145649 | Semiconductor devices with low parasitic capacitance | Haining Yang | 2021-10-12 |
| 10847507 | Contact liner to enable different CPP devices | Stanley Seungchul Song, Jie Deng, Giridhar Nallapati | 2020-11-24 |
| 10833017 | Contact for semiconductor device | Yanxiang Liu, Haining Yang, Youseok Suh, Jihong Choi | 2020-11-10 |
| 10686031 | Finger metal-oxide-metal (FMOM) capacitor | Peijie Feng, Ye Lu, Giridhar Nallapati | 2020-06-16 |
| 10665678 | Transistor with fluorinated graphene spacer | Ye Lu, Bin Yang, Lixin Ge, Yun Yue | 2020-05-26 |
| 10651122 | Integrated circuit (IC) interconnect structure having a metal layer with asymmetric metal line-dielectric structures supporting self-aligned vertical interconnect accesses (VIAS) | Giridhar Nallapati, Periannan Chidambaram | 2020-05-12 |