GN

Giridhar Nallapati

QU Qualcomm: 22 patents #1,021 of 12,104Top 9%
📍 San Diego, CA: #1,893 of 23,606 inventorsTop 9%
🗺 California: #25,620 of 386,348 inventorsTop 7%
Overall (All Time): #188,036 of 4,157,543Top 5%
22
Patents All Time

Issued Patents All Time

Showing 1–22 of 22 patents

Patent #TitleCo-InventorsDate
12342595 Transistor cell with self-aligned gate contact Junjing Bao, John Jianhong Zhu 2025-06-24
12218041 Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate for interfacing an IC chip(s) to a package substrate, and related methods Jihong Choi, William Stone, Jianwen Xu, Jonghae Kim, Periannan Chidambaram +1 more 2025-02-04
11973019 Deep trench capacitors in an inter-layer medium on an interconnect layer of an integrated circuit die and related methods Jihong Choi, Stanley Seungchul Song, Periannan Chidambaram 2024-04-30
11973020 Metal-insulator-metal capacitor with top contact John Jianhong Zhu, Lixin Ge 2024-04-30
11942414 Integrated circuits (ICs) employing directly coupled metal lines between vertically-adjacent interconnect layers for reduced coupling resistance, and related methods John Jianhong Zhu, Junjing Bao 2024-03-26
11437379 Field-effect transistors (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals, and related complementary metal oxide semiconductor (CMOS) circuits Stanley Seungchul Song, Deepak Sharma, Bharani Chava, Hyeokjin Lim, Peijie Feng +6 more 2022-09-06
11404373 Hybrid low resistance metal lines Junjing Bao, John Jianhong Zhu 2022-08-02
10847507 Contact liner to enable different CPP devices Junjing Bao, Stanley Seungchul Song, Jie Deng 2020-11-24
10686031 Finger metal-oxide-metal (FMOM) capacitor Peijie Feng, Junjing Bao, Ye Lu 2020-06-16
10651122 Integrated circuit (IC) interconnect structure having a metal layer with asymmetric metal line-dielectric structures supporting self-aligned vertical interconnect accesses (VIAS) Junjing Bao, Periannan Chidambaram 2020-05-12
10636737 Structure and method of metal wraparound for low via resistance Junjing Bao, Jie Deng, John Jianhong Zhu 2020-04-28
10418244 Modified self-aligned quadruple patterning (SAQP) processes using cut pattern masks to fabricate integrated circuit (IC) cells with reduced area Stanley Seungchul Song, Periannan Chidambaram 2019-09-17
10325979 High density and reliable vertical natural capacitors Junjing Bao, Jun Chen, Yangyang SUN, Stanley Seungchul Song 2019-06-18
10291211 Adaptive pulse generation circuits for clocking pulse latches with minimum hold time Stanley Seungchul Song, Seong-Ook Jung, Hanwool Jeong, Tae Woo Oh, Periannan Chidambaram 2019-05-14
10247617 Middle-of-line (MOL) metal resistor temperature sensors for localized temperature sensing of active semiconductor areas in integrated circuits (ICs) Lixin Ge, Periannan Chidambaram, Bin Yang, Jiefeng Lin, Bo Yu +3 more 2019-04-02
9818817 Metal-insulator-metal capacitor over conductive layer John Jianhong Zhu, P R Chidambaram, Choh Fei Yeap 2017-11-14
9287347 Metal-insulator-metal capacitor under redistribution layer John Jianhong Zhu, P R Chidambaram, Choh Fei Yeap 2016-03-15
9245971 Semiconductor device having high mobility channel Bin Yang, P R Chidambaram, John Jianhong Zhu, Jihong Choi, Da Yang +4 more 2016-01-26
9070551 Method and apparatus for a diffusion bridged cell library Benjamin J. Bowers, James W. Hayward, Charanya Gopal, Gregory Christopher Burda, Robert J. Bucki +3 more 2015-06-30
9024418 Local interconnect structures for high density John Jianhong Zhu, PR Chidambaram 2015-05-05
8836040 Shared-diffusion standard cell architecture Pratyush Kamal, Esin Terzioglu, Foua Vang, Prayag Bhanubhai Patel, Animesh Datta 2014-09-16
8782576 Method and apparatus for a diffusion bridged cell library Benjamin J. Bowers, James W. Hayward, Charanya Gopal, Gregory Christopher Burda, Robert J. Bucki +3 more 2014-07-15