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Vertical power grid standard cell architecture |
Bharani Chava, Foua Vang, Seung H. Kang, Venugopal Boynapalli |
2023-07-25 |
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Field-effect transistors (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals, and related complementary metal oxide semiconductor (CMOS) circuits |
Stanley Seungchul Song, Deepak Sharma, Bharani Chava, Peijie Feng, Seung H. Kang +6 more |
2022-09-06 |
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Circuits employing a back side-front side connection structure for coupling back side routing to front side routing, and related complementary metal oxide semiconductor (CMOS) circuits and methods |
Stanley Seungchul Song, Foua Vang, Seung H. Kang |
2022-08-02 |
| 11290109 |
Multibit multi-height cell to improve pin accessibility |
Foua Vang, Seung H. Kang, Venugopal Boynapalli, Shitiz Arora |
2022-03-29 |
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Multiple via structure for high performance standard cells |
Satyanarayana Sahu, Xiangdong Chen, Venugopal Boynapalli, Mickael Malabry, Mukul Gupta |
2021-09-28 |
| 10965289 |
Metal oxide semiconductor device of an integrated circuit |
Satyanarayana Sahu, Xiangdong Chen, Venugopal Boynapalli, Mickael Malabry, Mukul Gupta |
2021-03-30 |
| 10784345 |
Standard cell architecture for gate tie-off |
Xiangdong Chen, Venugopal Boynapalli |
2020-09-22 |
| 10777640 |
Standard cell architecture for gate tie-off |
Xiangdong Chen, Venugopal Boynapalli |
2020-09-15 |
| 10692808 |
High performance cell design in a technology with high density metal routing |
Renukprasad HIREMATH, Foua Vang, Xiangdong Chen, Venugopal Boynapalli |
2020-06-23 |
| 10605859 |
Visible alignment markers/landmarks for CAD-to-silicon backside image alignment |
Rami Fathy Salem, Lesly Zaren Venturina Endrinal, Hadi Bunnalim, Robert Kim, Lavakumar Ranganathan +1 more |
2020-03-31 |
| 10600866 |
Standard cell architecture for gate tie-off |
Xiangdong Chen, Venugopal Boynapalli |
2020-03-24 |
| 10490543 |
Placement methodology to remove filler |
Xiangdong Chen, Sorin Adrian Dobre, Venugopal Boynapalli |
2019-11-26 |
| 10236886 |
Multiple via structure for high performance standard cells |
Satyanarayana Sahu, Xiangdong Chen, Venugopal Boynapalli, Mickael Malabry, Mukul Gupta |
2019-03-19 |
| 10175571 |
Hybrid coloring methodology for multi-pattern technology |
Xiangdong Chen, Ohsang Kwon, Mickael Malabry, Jingwei Zhang, Raymond George Stephany +5 more |
2019-01-08 |
| 9960231 |
Standard cell architecture for parasitic resistance reduction |
Xiangdong Chen, Satyanarayana Sahu, Venugopal Boynapalli |
2018-05-01 |
| 9935100 |
Power rail inbound middle of line (MOL) routing |
Zhengyu Duan, Qi Ye, Mickael Malabry |
2018-04-03 |
| 9831272 |
Metal oxide semiconductor cell device architecture with mixed diffusion break isolation trenches |
Xiangdong Chen, Venugopal Boynapalli, Satyanarayana Sahu, Mukul Gupta |
2017-11-28 |
| 9577639 |
Source separated cell |
Satyanarayana Sahu, Xiangdong Chen, Venugopal Boynapalli, Mukul Gupta, Hananel Kang +2 more |
2017-02-21 |