Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11508725 | Layout construction for addressing electromigration | Seid Hadi Rasouli, Michael Brunolli, Christine Hau-Riege, Mickael Malabry, Sucheta Kumar Harish +4 more | 2022-11-22 |
| 11437375 | Layout construction for addressing electromigration | Seid Hadi Rasouli, Ohsang Kwon | 2022-09-06 |
| 10600785 | Layout construction for addressing electromigration | Seid Hadi Rasouli, Michael Brunolli, Christine Hau-Riege, Mickael Malabry, Sucheta Kumar Harish +4 more | 2020-03-24 |
| 10580774 | Layout construction for addressing electromigration | Seid Hadi Rasouli, Ohsang Kwon | 2020-03-03 |
| 10074609 | Layout construction for addressing electromigration | Seid Hadi Rasouli, Ohsang Kwon | 2018-09-11 |
| 10033359 | Area efficient flip-flop with improved scan hold-margin | Qi Ye | 2018-07-24 |
| 9979394 | Pulse-generator | Qi Ye, Venkatasubramanian Narayanan, Venugopal Boynapalli | 2018-05-22 |
| 9972624 | Layout construction for addressing electromigration | Seid Hadi Rasouli, Michael Brunolli, Christine Hau-Riege, Mickael Malabry, Sucheta Kumar Harish +4 more | 2018-05-15 |
| 9966953 | Low clock power data-gated flip-flop | Qi Ye, Bo Pang | 2018-05-08 |
| 9875209 | Synchronous data-link throughput enhancement technique based on data signal duty-cycle and phase modulation/demodulation | Lalan Jee Mishra, Dexter Tamio Chun | 2018-01-23 |
| 9786663 | Layout construction for addressing electromigration | Seid Hadi Rasouli, Ohsang Kwon | 2017-10-10 |
| 9678154 | Circuit techniques for efficient scan hold path design | Qi Ye, Steven James Dillen | 2017-06-13 |
| 9673786 | Flip-flop with reduced retention voltage | Seid Hadi Rasouli, Jay M. Shah, Martin Saint-Laurent, Peeyush Kumar Parkar, Sachin Bapat +3 more | 2017-06-06 |
| 9584121 | Compact design of scan latch | Qi Ye, Zhengyu Duan, Steven James Dillen | 2017-02-28 |
| 9577635 | Clock-gating cell with low area, low power, and low setup time | Seid Hadi Rasouli, Steven James Dillen | 2017-02-21 |
| 9564881 | Area-efficient metal-programmable pulse latch design | Qi Ye, Steven James Dillen, Zhengyu Duan, Satyanarayana Sahu, Praveen Narendranath | 2017-02-07 |
| 9318476 | High performance standard cell with continuous oxide definition and characterized leakage current | Xiangdong Chen, Ohsang Kwon, Foua Vang, Seid Hadi Rasouli | 2016-04-19 |
| 9190405 | Digital circuit design with semi-continuous diffusion standard cell | Xiangdong Chen, Ohsang Kwon, Satyanarayana Sahu, Divya Gangadharan, Chih-Iung Kao +2 more | 2015-11-17 |
| 9083325 | Low overhead hold-violation fixing solution using metal-programable cells | Qi Ye, Chih-Lung Kao | 2015-07-14 |
| 9070552 | Adaptive standard cell architecture and layout techniques for low area digital SoC | Jay M. Shah, Kamesh MEDISETTI, Vijayalakshmi RANGANNA | 2015-06-30 |
| 9024658 | Circuit and layout techniques for flop tray area and power otimization | Jay M. Shah, Chethan Swamynathan | 2015-05-05 |
| 9020084 | High frequency synchronizer | Seid Hadi Rasouli, Saravanan Marimuthu, Ohsang Kwon | 2015-04-28 |
| 8836040 | Shared-diffusion standard cell architecture | Pratyush Kamal, Esin Terzioglu, Foua Vang, Prayag Bhanubhai Patel, Giridhar Nallapati | 2014-09-16 |
| 8584075 | Method and apparatus for characterizing and reducing proximity effect on cell electrical characteristics | Pratyush Kamal, Prayag Bhanubhai Patel, Xiaonan Zhang | 2013-11-12 |
| 8487658 | Compact and robust level shifter layout design | William Goodall, III | 2013-07-16 |