Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10141297 | Integrated device comprising device level cells with variable sizes for heat dissipation around hotspots | Palkesh Jain, Mehdi Saeidi, Jon James Anderson, Richard E. Wunderlich | 2018-11-27 |
| 9024658 | Circuit and layout techniques for flop tray area and power otimization | Jay M. Shah, Animesh Datta | 2015-05-05 |
| 8610176 | Standard cell architecture using double poly patterning for multi VT devices | Prayag Bhanubhai Patel, Pratyush Kamal, Foua Vang, Chock Hing Gan, PR Chidambaram | 2013-12-17 |