| 9673786 |
Flip-flop with reduced retention voltage |
Seid Hadi Rasouli, Animesh Datta, Martin Saint-Laurent, Peeyush Kumar Parkar, Sachin Bapat +3 more |
2017-06-06 |
| 9589658 |
Disturb free bitcell and array |
Navin Agarwal, Aditya S. Auyisetty, Balaji Jayaraman, Thejas Kempanna, Toshiaki Kirihata +4 more |
2017-03-07 |
| 9431289 |
Method and structure to reduce FET threshold voltage shift due to oxygen diffusion |
Christopher V. Baiocco, Michael P. Chudzik, Deleep R. Nair |
2016-08-30 |
| 9397101 |
Stacked common gate finFET devices for area optimization |
Harikrishna Chintarlapalli Reddy, Ananth Haliyur Gopalakrishna |
2016-07-19 |
| 9196707 |
Oxygen scavenging spacer for a gate electrode |
Michael P. Chudzik, Deleep R. Nair, Vijay Narayanan, Carl Radens |
2015-11-24 |
| 9093495 |
Method and structure to reduce FET threshold voltage shift due to oxygen diffusion |
Christopher V. Baiocco, Michael P. Chudzik, Deleep R. Nair |
2015-07-28 |
| 9070552 |
Adaptive standard cell architecture and layout techniques for low area digital SoC |
Kamesh MEDISETTI, Vijayalakshmi RANGANNA, Animesh Datta |
2015-06-30 |
| 9059211 |
Oxygen scavenging spacer for a gate electrode |
Michael P. Chudzik, Deleep R. Nair, Vijay Narayanan, Carl Radens |
2015-06-16 |
| 9024658 |
Circuit and layout techniques for flop tray area and power otimization |
Chethan Swamynathan, Animesh Datta |
2015-05-05 |
| 8564074 |
Self-limiting oxygen seal for high-K dielectric and design structure |
Terence B. Hook, Vijay Narayanan, Melanie J. Sherony, Kenneth J. Stein, Helen Wang +1 more |
2013-10-22 |
