Issued Patents All Time
Showing 1–25 of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11347256 | Apparatus and methods for reducing clock-ungating induced voltage droop | Lam Ho, Carlos Andres Rodriguez Ancer, Bhavin Shah | 2022-05-31 |
| 11047946 | Differential current sensing with robust path, voltage offset removal and process, voltage, temperature (PVT) tolerance | Nam V. Dang, Rajeev Jain, Swarna L. Navubothu, Alan Lewis, Tung Nang Pham +3 more | 2021-06-29 |
| 10890937 | Apparatus and methods for reducing clock-ungating induced voltage droop | Lam Ho, Carlos Andres Rodriguez Ancer, Bhavin Shah | 2021-01-12 |
| 10409317 | Apparatus and methods for reducing clock-ungating induced voltage droop | Lam Ho, Carlos Andres Rodriguez Ancer, Bhavin Shah | 2019-09-10 |
| 10309838 | Temporal temperature sensor position offset error correction | Ali Akbar Merrikh, Mohammad GHASEMAZAR, Rajit Chandra, Mohamed Waleed Allam | 2019-06-04 |
| 10152101 | Controlling voltage deviations in processing systems | Eric W. Mahurin, Sanjay Bhagawan Patil | 2018-12-11 |
| 10133285 | Voltage droop control | Sanjay Bhagawan Patil, Daniel Stasiak, Rui Li, Bin Liang, Sei Seung Yoon +1 more | 2018-11-20 |
| 9851730 | Voltage droop control | Sanjay Bhagawan Patil, Daniel Stasiak, Rui Li, Bin Liang, Sei Seung Yoon +1 more | 2017-12-26 |
| 9804650 | Supply voltage node coupling using a switch | Sanjay Bhagawan Patil, Daniel Stasiak | 2017-10-31 |
| 9785601 | System and method for reducing cross coupling effects | Baker Mohammad, Paul Bassett | 2017-10-10 |
| 9673786 | Flip-flop with reduced retention voltage | Seid Hadi Rasouli, Animesh Datta, Jay M. Shah, Peeyush Kumar Parkar, Sachin Bapat +3 more | 2017-06-06 |
| 9417643 | Voltage regulator with variable impedance element | Yuhe Wang | 2016-08-16 |
| 9348402 | Multiple critical paths having different threshold voltages in a single processor core | Joseph Victor Zanotelli | 2016-05-24 |
| 9093995 | Length-of-diffusion protected circuit and method of design | Kashyap Ramachandra Bellur, Harikrishna Chintarlapalli Reddy, Pratyush Kamal, Prayag Bhanubhai Patel, Esin Terzioglu | 2015-07-28 |
| 8995207 | Data storage for voltage domain crossings | Christopher Edward Koob, Jen-Tsung Lin, Manojkumar Pyla | 2015-03-31 |
| 8994458 | Oscillator based frequency locked loop | — | 2015-03-31 |
| 8397238 | Thread allocation and clock cycle adjustment in an interleaved multi-threaded processor | Suresh K. Venkumahanti, Lucian Codrescu, Baker Mohammad | 2013-03-12 |
| 8030982 | Systems and methods using improved clock gating cells | Animesh Datta, Varun Verma, Prayag Bhanubhai Patel | 2011-10-04 |
| 7996695 | Circuits and methods for sleep state leakage current reduction | Jentsung Lin | 2011-08-09 |
| 7992062 | Logic device and method supporting scan test | Paul Bassett, Prayag Bhanubhai Patel | 2011-08-02 |
| 7911239 | Glitch-free clock signal multiplexer circuit and method of operation | Yan Zhang | 2011-03-22 |
| 7902878 | Clock gating system and method | Bassam J. Mohd, Paul Bassett | 2011-03-08 |
| 7816960 | Circuit device and method of measuring clock jitter | Boris Andreev, Paul Bassett | 2010-10-19 |
| 7746137 | Sequential circuit element including a single clocked transistor | Baker Mohammad, Paul Bassett | 2010-06-29 |
| 7724058 | Latch structure and self-adjusting pulse generator using the latch | Paul Bassett | 2010-05-25 |