Issued Patents All Time
Showing 1–25 of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11663011 | System and method of VLIW instruction processing using reduced-width VLIW processor | Peter G. Sassone, Christopher Edward Koob | 2023-05-30 |
| 11599625 | Techniques for instruction perturbation for improved device security | Arvind Krishnaswamy, Charles Joseph Tabony | 2023-03-07 |
| 11200058 | Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer-readable media | Stephen Robert Shannon, Lin Wang | 2021-12-14 |
| 10719325 | System and method of VLIW instruction processing using reduced-width VLIW processor | Peter G. Sassone, Christopher Edward Koob | 2020-07-21 |
| 10625752 | System and method for online functional testing for error-correcting code function | Mohammad Reza Kakoee, Rahul Gulati, Eric W. Mahurin, Dexter Tamio Chun | 2020-04-21 |
| 10353447 | Current in-rush mitigation for power-up of embedded memories | Harmander Singh, Sebastien Weyland | 2019-07-16 |
| 10068645 | Multiple cycle search content addressable memory | Kim Yaw Tong, Fadi Adel Hamdan, Kun Ma | 2018-09-04 |
| 10055227 | Using the least significant bits of a called function's address to switch processor modes | Charles Joseph Tabony, Erich James Plondke, Lucian Codrescu, Evandro Menezes | 2018-08-21 |
| 10025711 | Hybrid write-through/write-back cache policy managers, and related systems and methods | Peter G. Sassone, Christopher Edward Koob, Dana Michelle Vantrease, Lucian Codrescu | 2018-07-17 |
| 10007613 | Reconfigurable fetch pipeline | Stephen Robert Shannon | 2018-06-26 |
| 9928159 | System and method to select a packet format based on a number of executed threads | Prasanna Kumar Balasundaram | 2018-03-27 |
| 9824013 | Per thread cacheline allocation mechanism in shared partitioned caches in multi-threaded processors | Christopher Edward Koob, Ajay Anant Ingle, Lucian Codrescu | 2017-11-21 |
| 9804969 | Speculative addressing using a virtual address-to-physical address page crossing buffer | Jiajin Tu, Phillip M. Jones | 2017-10-31 |
| 9715392 | Multiple clustered very long instruction word processing core | Ankit Ghiya, Peter G. Sassone, Lucian Codrescu, Suman Mamidi | 2017-07-25 |
| 9678754 | System and method of processing hierarchical very long instruction packets | Lucian Codrescu, Erich James Plondke, Ajay Anant Ingle, Charles Joseph Tabony | 2017-06-13 |
| 9678758 | Coprocessor for out-of-order loads | Lucian Codrescu, Christopher Edward Koob, Eric W. Mahurin | 2017-06-13 |
| 9552033 | Latency-based power mode units for controlling power modes of processor cores, and related methods and systems | Peter G. Sassone, Sanjay Bhagawan Patil | 2017-01-24 |
| 9529727 | Reconfigurable fetch pipeline | Stephen Robert Shannon | 2016-12-27 |
| 9489204 | Method and apparatus for precalculating a direct branch partial target address during a misprediction correction process | Jiajin Tu, Brian R. Mestan | 2016-11-08 |
| 9384825 | Multi-port memory circuits | Jentsung Lin, Paul Bassett | 2016-07-05 |
| 9367468 | Data cache way prediction | Peter G. Sassone, Lucian Codrescu | 2016-06-14 |
| 9361109 | System and method to evaluate a data value as an instruction | Lucian Codrescu, Erich James Plondke | 2016-06-07 |
| 9304932 | Instruction cache having a multi-bit way prediction mask | Peter G. Sassone, Lucian Codrescu | 2016-04-05 |
| 9208102 | Overlap checking for a translation lookaside buffer (TLB) | Erich James Plondke, Lucian Codrescu, Shane M. Mahon, Rahul R. Toley, Fadi Adel Hamdan | 2015-12-08 |
| 9122486 | Bimodal branch predictor encoded in a branch instruction | Lucian Codrescu, Stephen Robert Shannon, Lin Wang, Phillip M. Jones, Daisy T. Palal +1 more | 2015-09-01 |